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基于 HfO 忆阻器尖峰神经元的混合卷积神经网络的手写数字识别。

Handwritten-Digit Recognition by Hybrid Convolutional Neural Network based on HfO Memristive Spiking-Neuron.

机构信息

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, 610054, P. R. China.

School of Materials and Energy, Guangdong University of Technology, Guangzhou, 510006, P. R. China.

出版信息

Sci Rep. 2018 Aug 22;8(1):12546. doi: 10.1038/s41598-018-30768-0.

DOI:10.1038/s41598-018-30768-0
PMID:30135449
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC6105732/
Abstract

Although there is a huge progress in complementary-metal-oxide-semiconductor (CMOS) technology, construction of an artificial neural network using CMOS technology to realize the functionality comparable with that of human cerebral cortex containing 10-10 neurons is still of great challenge. Recently, phase change memristor neuron has been proposed to realize a human-brain level neural network operating at a high speed while consuming a small amount of power and having a high integration density. Although memristor neuron can be scaled down to nanometer, integration of 10-10 neurons still faces many problems in circuit complexity, chip area, power consumption, etc. In this work, we propose a CMOS compatible HfO memristor neuron that can be well integrated with silicon circuits. A hybrid Convolutional Neural Network (CNN) based on the HfO memristor neuron is proposed and constructed. In the hybrid CNN, one memristive neuron can behave as multiple physical neurons based on the Time Division Multiplexing Access (TDMA) technique. Handwritten digit recognition is demonstrated in the hybrid CNN with a memristive neuron acting as 784 physical neurons. This work paves the way towards substantially shrinking the amount of neurons required in hardware and realization of more complex or even human cerebral cortex level memristive neural networks.

摘要

尽管互补金属氧化物半导体 (CMOS) 技术取得了巨大的进步,但使用 CMOS 技术构建一个人工神经网络,使其实现与包含 10-10 个神经元的人类大脑皮层相当的功能仍然具有很大的挑战性。最近,相变存储器神经元被提出用于实现高速运行、低功耗和高集成密度的人脑水平神经网络。虽然忆阻器神经元可以缩小到纳米级,但要集成 10-10 个神经元,在电路复杂性、芯片面积、功耗等方面仍然面临许多问题。在这项工作中,我们提出了一种与 CMOS 兼容的 HfO 忆阻器神经元,它可以与硅电路很好地集成。提出并构建了一种基于 HfO 忆阻器神经元的混合卷积神经网络 (CNN)。在混合 CNN 中,一个忆阻器神经元可以基于时分多址 (TDMA) 技术表现为多个物理神经元。在混合 CNN 中,用一个忆阻器神经元模拟 784 个物理神经元,对手写数字进行了识别。这项工作为在硬件中大大减少所需神经元的数量以及实现更复杂甚至是人类大脑皮层水平的忆阻神经网络铺平了道路。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/16fc2d4f6943/41598_2018_30768_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/0ad1b35e851a/41598_2018_30768_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/1897bbdf98d7/41598_2018_30768_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/172273469734/41598_2018_30768_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/16fc2d4f6943/41598_2018_30768_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/0ad1b35e851a/41598_2018_30768_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/1897bbdf98d7/41598_2018_30768_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/172273469734/41598_2018_30768_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/5c40/6105732/16fc2d4f6943/41598_2018_30768_Fig4_HTML.jpg

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