Imec, 3001 Heverlee, Belgium.
Department of Electronics and informatics (ETRO), Vrije Universiteit Brussel, 1050 Brussels, Belgium.
Sensors (Basel). 2018 Oct 30;18(11):3683. doi: 10.3390/s18113683.
This paper presents an in-situ storage topology for ultra-high-speed burst mode imagers, enabling low noise operation while keeping a high frame depth. The proposed pixel architecture contains a 4T pinned photodiode, a correlated double sampling (CDS) amplification stage, and an in-situ memory bank. Focusing on the sampling noise, the system level trade-off of the proposed pixel architecture is discussed, showing its advantages on the noise, power, and scaling capability. Integrated with an AC coupling CDS stage, the amplification is obtained by exploiting the strong capacitance to the voltage relation of a single NMOS transistor. A comprehensive noise model is developed for optimizing the trade-off between the area and noise. As a proof-of-concept, a prototype imager with a 30 µm pixel pitch was fabricated in a CMOS 130 nm technology. A 108-cell memory bank is implemented allowing dense layout and parallel readout. Two types of CDS amplification stages were investigated. Despite the limited memory capacitance of 10 fF/cell, the photon transfer curves of both pixel types were measured over different operation speeds up to 20 Mfps showing a noise performance of 8.4 e.
本文提出了一种用于超高速度突发模式成像器的原位存储拓扑结构，在保持高帧深度的同时实现低噪声操作。所提出的像素架构包含一个 4T 固定光电二极管、相关双采样 (CDS) 放大级和原位存储库。本文重点讨论了所提出的像素架构的系统级权衡，展示了其在噪声、功率和缩放能力方面的优势。与交流耦合 CDS 级集成，通过利用单个 NMOS 晶体管的电容与电压关系来实现放大。开发了一个全面的噪声模型，以优化面积和噪声之间的权衡。作为概念验证，使用 CMOS 130nm 技术制造了具有 30μm 像素间距的原型成像器。实现了 108 个单元的存储库，允许密集布局和并行读出。研究了两种类型的 CDS 放大级。尽管每个单元的存储电容有限为 10fF，但这两种像素类型的光子转移曲线都在不同的操作速度下进行了测量，最高可达 20Mfps，噪声性能为 8.4e。
