Liu Kefei, Cui Xiaoxin, Zhong Yi, Kuang Yisong, Wang Yuan, Tang Huajin, Huang Ru
Institute of Microelectronics, Peking University, Beijing, China.
National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beijing, China.
Front Neurosci. 2019 Aug 9;13:835. doi: 10.3389/fnins.2019.00835. eCollection 2019.
Simulating human brain with hardware has been an attractive project for many years, since memory is one of the fundamental functions of our brains. Several memory models have been proposed up to now in order to unveil how the memory is organized in the brain. In this paper, we adopt spatio-temporal memory (STM) model, in which both associative memory and episodic memory are analyzed and emulated, as the reference of our hardware network architecture. Furthermore, some reasonable adaptations are carried out for the hardware implementation. We finally implement this memory model on FPGA, and additional experiments are performed to fine tune the parameters of our network deployed on FPGA.
多年来，用硬件模拟人类大脑一直是一个颇具吸引力的项目，因为记忆是我们大脑的基本功能之一。为了揭示记忆在大脑中的组织方式，到目前为止已经提出了几种记忆模型。在本文中，我们采用时空记忆（STM）模型，其中对联想记忆和情景记忆都进行了分析和模拟，作为我们硬件网络架构的参考。此外，针对硬件实现进行了一些合理的调整。我们最终在现场可编程门阵列（FPGA）上实现了这个记忆模型，并进行了额外的实验来微调部署在FPGA上的网络参数。
