Bapat Aniruddha, Eldredge Zachary, Garrison James R, Deshpande Abhinav, Chong Frederic T, Gorshkov Alexey V
Joint Center for Quantum Information and Computer Science, NIST/University of Maryland, College Park, Maryland 20742, USA.
Joint Quantum Institute, NIST/University of Maryland, College Park, Maryland 20742, USA.
Phys Rev A (Coll Park). 2018;98. doi: 10.1103/PhysRevA.98.062328.
The construction of large-scale quantum computers will require modular architectures that allow physical resources to be localized in easy-to-manage packages. In this work we examine the impact of different graph structures on the preparation of entangled states. We begin by explaining a formal framework, the hierarchical product, in which modular graphs can be easily constructed. This framework naturally leads us to suggest a class of graphs, which we dub hierarchies. We argue that such graphs have favorable properties for quantum information processing, such as a small diameter and small total edge weight, and use the concept of Pareto efficiency to identify promising quantum graph architectures. We present numerical and analytical results on the speed at which large entangled states can be created on nearest-neighbor grids and hierarchy graphs. We also present a scheme for performing circuit placement-the translation from circuit diagrams to machine qubits-on quantum systems whose connectivity is described by hierarchies.
大规模量子计算机的构建将需要模块化架构，这种架构能使物理资源被定位在易于管理的组件中。在这项工作中，我们研究了不同图结构对纠缠态制备的影响。我们首先解释一个形式框架——层次积，在这个框架中可以轻松构建模块化图。这个框架自然地引导我们提出一类图，我们将其称为层次结构。我们认为这类图对于量子信息处理具有有利特性，比如小直径和小的总边权重，并使用帕累托效率的概念来识别有前景的量子图架构。我们给出了关于在最近邻网格和层次结构图上创建大纠缠态的速度的数值和分析结果。我们还提出了一种在其连通性由层次结构描述的量子系统上进行电路布局的方案——从电路图到机器量子比特的转换。
