CMOS-compatible synaptic transistor gated by chitosan electrolyte-TaO hybrid electric double layer.

This study proposes a hybrid electric double layer (EDL) with complementary metal-oxide semiconductor (CMOS) process compatibility by stacking a chitosan electrolyte and a TaO high-k dielectric thin film. Bio-inspired synaptic transistors with excellent electrical stability were fabricated using the proposed hybrid EDL for the gate dielectric layer. The TaO high-k dielectric layer with high chemical resistance, thermal stability, and mechanical strength enables CMOS-compatible patterning processes on biocompatible organic polymer chitosan electrolytes. This technique achieved ion-conduction from the chitosan electrolyte to the In-Ga-Zn oxide (IGZO) channel layer. The on/off current ratio, subthreshold voltage swing, and the field-effect mobility of the fabricated IGZO EDL transistors (EDLTs) exhibited excellent electrical properties of 1.80 × 10, 96 mV/dec, and 3.73 cm/V·s, respectively. A resistor-loaded inverter was constructed by connecting an IGZO EDLT with a load resistor (400 MΩ) in series. This demonstrated good inverter action and responded to the square-wave input signals. Synaptic behaviours such as the hysteresis window and excitatory post-synaptic current (EPSC) variations were evaluated for different DC gate voltage sweep ranges and different AC gate spike stimuli, respectively. Therefore, the proposed organic-inorganic hybrid EDL is expected to be useful for implementing an extremely compact neural architecture system.