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用于集成CMOS逻辑的平面硅纳米线意外的磷掺杂工艺

Unexpected phosphorus doping routine of planar silicon nanowires for integrating CMOS logics.

作者信息

Sun Ying, Qian Wentao, Liu Shuaishuai, Dong Taige, Wang Junzhuan, Xu Jun, Chen Kunji, Yu Linwei

机构信息

School of Electronics Science and Engineering/National Laboratory of Solid-State Microstructures, Nanjing University, 210093 Nanjing, P. R. China.

出版信息

Nanoscale. 2021 Sep 17;13(35):15031-15037. doi: 10.1039/d1nr03014k.

Abstract

Complementary doping control in silicon nanowire (SiNW) channels is crucial for the construction of high-performance CMOS logics. Though planar in-plane solid-liquid-solid (IPSLS) growth, with an amorphous Si (a-Si) thin film as a precursor, has demonstrated a precise and scalable integration of orderly SiNWs, a complementary and tunable n-type doping has not been accomplished. This has been hindered by the fact that the phosphorus (P) gas dopants will react with the indium (In) catalyst droplet to form insoluble InP precipitates. Nevertheless, we herein report on an unexpected discovery that the P dopants first incorporated into the a-Si matrix can easily diffuse over the In catalyst droplets, without forming an InP compound, and thus reverse continuously the initial p-type SiNWs into an n-type channel. Uniform and efficient doping effects have been confirmed by both atomic probe tomography mapping and the transfer properties of SiNW FETs, which demonstrate a steep subthreshold swing of 105 mV dec, an on/off ratio of >10 and an electron mobility of 142 cm V s. Finally, true CMOS inverters are successfully demonstrated based on the closely-packed SiNW channels of distinct doping polarities, indicating a new convenient and highly efficient doping routine to construct more advanced SiNW logics and sensors.

摘要

硅纳米线(SiNW)沟道中的互补掺杂控制对于构建高性能CMOS逻辑至关重要。尽管以非晶硅(a-Si)薄膜为前驱体的平面面内固液固(IPSLS)生长已证明有序SiNWs能够精确且可扩展地集成,但尚未实现互补且可调的n型掺杂。这一进展受到磷(P)气体掺杂剂会与铟(In)催化剂液滴反应形成不溶性InP沉淀物这一事实的阻碍。然而,我们在此报告一项意外发现,即首先掺入a-Si基体中的P掺杂剂能够轻松扩散过In催化剂液滴,而不形成InP化合物,从而将初始的p型SiNWs连续反转成n型沟道。通过原子探针断层扫描映射和SiNW场效应晶体管的传输特性均证实了均匀且高效的掺杂效果,其展示出105 mV/dec的陡峭亚阈值摆幅、>10的开/关比以及142 cm²/V·s的电子迁移率。最后,基于不同掺杂极性的紧密堆积SiNW沟道成功展示了真正的CMOS反相器,这表明一种构建更先进SiNW逻辑和传感器的新型便捷且高效的掺杂方法。

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