Cherala Anshuman, Pandya Parth N, Liechti Kenneth M, Sreenivasan S V
NASCENT Engineering Research Center, The University of Texas at Austin, Austin, TX USA.
Microsyst Nanoeng. 2021 Feb 1;7:13. doi: 10.1038/s41378-020-00225-y. eCollection 2021.
Emerging nanoscale applications in energy, electronics, optics, and medicine can exhibit enhanced performance by incorporating nanoshaped structures (nanoshape structures here are defined as shapes enabled by sharp corners with radius of curvature < 5 nm). Nanoshaped fabrication at high-throughput is well beyond the capabilities of advanced optical lithography. Although the highest-resolution e-beams and large-area e-beams have a resolution limit of 5 and 18 nm half-pitch lines or 20 nm half-pitch holes, respectively, their low throughput necessitates finding other fabrication techniques. By using nanoimprint lithography followed by metal-assisted chemical etching, diamond-like nanoshapes with ~3 nm radius corners and 100 nm half-pitch over large areas have been previously demonstrated to improve the nanowire capacitor performance (by ~90%). In future dynamic random-access memory (DRAM) nodes (with DRAM being an exemplar CMOS application), the implementation of nanowire capacitors scaled to <15 nm half-pitch is required. To scale nanoshape imprint lithography down to these half-pitch values, the previously established atomistic simulation framework indicates that the current imprint resist materials are unable to retain the nanoshape structures needed for DRAM capacitors. In this study, the previous simulation framework is extended to study improved shape retention by varying the resist formulations and by introducing novel bridge structures in nanoshape imprinting. This simulation study has demonstrated viable approaches to sub-10 nm nanoshaped imprinting with good shape retention, which are matched by experimental data.
在能源、电子、光学和医学领域新兴的纳米级应用，通过纳入纳米形状结构（这里的纳米形状结构定义为具有曲率半径<5nm的尖角所形成的形状）可展现出增强的性能。高通量的纳米形状制造远远超出了先进光学光刻的能力范围。尽管最高分辨率的电子束光刻和大面积电子束光刻的分辨率极限分别为半间距线5nm和18nm或半间距孔20nm，但其低通量使得必须寻找其他制造技术。通过使用纳米压印光刻技术，随后进行金属辅助化学蚀刻，先前已证明在大面积上具有约3nm半径角和100nm半间距的类金刚石纳米形状可改善纳米线电容器的性能（提高约90%）。在未来的动态随机存取存储器（DRAM）节点（DRAM是典型的CMOS应用）中，需要实现缩放到<15nm半间距的纳米线电容器。为了将纳米形状压印光刻缩放到这些半间距值，先前建立的原子模拟框架表明，当前的压印抗蚀剂材料无法保留DRAM电容器所需的纳米形状结构。在本研究中，扩展了先前的模拟框架，以研究通过改变抗蚀剂配方和在纳米形状压印中引入新型桥结构来改善形状保留。该模拟研究已证明了可行的方法来实现具有良好形状保留的亚10nm纳米形状压印，这与实验数据相匹配。
