Mah Siew Kien, Ker Pin Jern, Ahmad Ibrahim, Zainul Abidin Noor Faizah, Ali Gamel Mansur Mohammed
Institute of Sustainable Energy, Universiti Tenaga Nasional, Kajang 43000, Malaysia.
Department of Electrical Engineering, Nilai University, Nilai 71800, Malaysia.
Materials (Basel). 2021 Sep 30;14(19):5721. doi: 10.3390/ma14195721.
At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Moore's Law. The need to satisfy performance requirements and to overcome the limitations of planar bulk transistor to scales below 22 nm led to the development of fully depleted silicon-on-insulator (FDSOI) and fin field-effect transistor (FinFET) technologies. The 28-nm wafer planar process is the most cost-effective, and scaling towards the sub-10 nm technology node involves the complex integration of new materials (Ge, III-V, graphene) and new device architectures. To date, planar transistors still command >50% of the transistor market and applications. This work aims to downscale a planar PMOS to a 14-nm gate length using LaO as the high-k dielectric material. The device was virtually fabricated and electrically characterized using SILVACO. Taguchi L9 and L27 were employed to study the process parameters' variability and interaction effects to optimize the process parameters to achieve the required output. The results obtained from simulation using the SILVACO tool show good agreement with the nominal values of PMOS threshold voltage () of -0.289 V ± 12.7% and of less than 10 A/µm, as projected by the International Technology Roadmap for Semiconductors (ITRS). Careful control of SiO formation at the Si interface and rapid annealing processing are required to achieve LaO thermal stability at the target equivalent oxide thickness (EOT). The effects of process variations on , and were investigated. The improved voltage scaling resulting from the lower value is associated with the increased due to the improved drain-induced barrier lowering as the gate length decreases. The performance of the 14-nm planar bulk PMOS is comparable to the performance of the FDSOI and FinFET technologies at the same gate length. The comparisons made with ITRS, the International Roadmap for Devices and Systems (IRDS), and the simulated and experimental data show good agreement and thus prove the validity of the developed model for PMOSs. Based on the results demonstrated, planar PMOSs could be a feasible alternative to FDSOI and FinFET in balancing the trade-off between performance and cost in the 14-nm process.
在90纳米节点处，由于克服漏电流增加方面存在挑战，晶体管小型化速率放缓。45纳米技术节点上高k/金属栅极技术的发明是在扩展摩尔定律方面向前迈出的巨大一步。为了满足性能要求并克服平面体晶体管在低于22纳米尺度下的局限性，促使了全耗尽绝缘体上硅（FDSOI）和鳍式场效应晶体管（FinFET）技术的发展。28纳米晶圆平面工艺是最具成本效益的，而向低于10纳米技术节点的扩展涉及新材料（锗、III-V族化合物、石墨烯）和新器件架构的复杂集成。迄今为止，平面晶体管仍占据着超过50%的晶体管市场及应用。这项工作旨在使用氧化镧作为高k介电材料，将平面PMOS缩小至14纳米栅长。该器件通过SILVACO进行了虚拟制造和电学特性表征。采用田口L9和L27方法来研究工艺参数的变异性和相互作用效应，以优化工艺参数从而实现所需输出。使用SILVACO工具进行模拟得到的结果与国际半导体技术路线图（ITRS）预测的PMOS阈值电压（）的标称值-0.289 V±12.7%以及小于10 A/μm的漏电流显示出良好的一致性。为了在目标等效氧化层厚度（EOT）下实现氧化镧的热稳定性，需要仔细控制硅界面处二氧化硅的形成以及快速退火工艺。研究了工艺变化对阈值电压、漏电流和驱动电流的影响。由于随着栅长减小漏极感应势垒降低得到改善，较低的漏电流值导致的电压缩放改善与驱动电流增加相关。14纳米平面体PMOS的性能与相同栅长下的FDSOI和FinFET技术的性能相当。与ITRS、国际器件与系统路线图（IRDS）以及模拟和实验数据进行的比较显示出良好的一致性，从而证明了所开发的PMOS模型的有效性。基于所展示的结果，在14纳米工艺中，平面PMOS在平衡性能和成本之间的权衡方面可能是FDSOI和FinFET的可行替代方案。
