Sheu Ming-Hwa, Tsai Chang-Ming, Tsai Ming-Yan, Hsia Shih-Chang, Morsalin S M Salahuddin, Lin Jin-Fa
Department of Electronic Engineering, National Yunlin University of Science and Technology, Douliu City 64002, Taiwan.
Department of Information and Communication Engineering, Chaoyang University of Technology, Wufeng District, Taichung City 413310, Taiwan.
Sensors (Basel). 2021 Oct 2;21(19):6591. doi: 10.3390/s21196591.
An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.
一种创新且稳定的基于脉冲神经网络（PNN）的10晶体管（10T）静态随机存取存储器（SRAM）架构已被设计用于低功耗位单元操作和亚阈值电压应用。所提出的设计具有以下特点：（a）基于脉冲控制的读辅助电路提供了一种动态读去耦方法，用于消除读干扰；（b）我们利用了写数据感知技术来切断下拉路径；（c）额外的写电流增强了操作期间的写能力。所提出的设计不仅解决了半选问题并提高了读静态噪声容限（RSNM），还提供了低泄漏功耗性能。基于台积电40纳米通用型互补金属氧化物半导体（GP CMOS）工艺技术实现了1-Kb SRAM宏（32行×32列）的设计架构。在300毫伏电源电压和10兆赫工作频率下，读功耗和写功耗分别为4.15微瓦和3.82微瓦，而平均能耗仅为0.39皮焦。
