Yoo Changhyun, Chang Jeesoo, Park Sugil, Kim Hyungyeong, Jeon Jongwook
Department of Electrical and Electronics Engineering, Konkuk University, Seoul 05029, Korea.
Data and Information Tech. (DIT) Center, Samsung Electronics, Hwasung-Si 18448, Korea.
Nanomaterials (Basel). 2022 Feb 9;12(4):591. doi: 10.3390/nano12040591.
In this study on multi-nanosheet field-effect transistor (mNS-FET)-one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension-3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 10 cm to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types-such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)-were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (I) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 10 cm, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.
在这项针对多纳米片场效应晶体管（mNS - FET）的研究中——mNS - FET是3纳米技术节点尺寸的全栅场效应晶体管（GAAFET）之一——采用了三维技术计算机辅助设计（3D TCAD），以从包括穿通阻挡（PTS）掺杂方案和底部氧化物（BO）底部隔离方案等选项中实现最佳的衬底泄漏降低，并且在使用mNS - FET的电路级动态操作中展现出了性能提升。无论底部隔离层是否存在，PTS掺杂浓度都需要大于5×10¹⁸ cm⁻³的高值，以减少栅极感应漏极泄漏（GIDL）。当底部隔离与PTS掺杂方案一起应用时，与仅应用PTS掺杂浓度相比，电容减小比导通电流减小更大。评估了这种晶体管特性对各种电路类型性能和能力的影响，如反相器环形振荡器（RO）、全加器（FA）电路和静态随机存取存储器（SRAM）。对于RO，同时应用BO和PTS掺杂可使在相同功耗下运行速度提高11.3%，或者在相同速度下功耗降低26.4%。对于FA，当同时应用BO和PTS时，在相同待机功耗下，功耗可降低6.45%，能量延迟积（EDP）降低21.4%，延迟降低16.8%。最后，对于SRAM，在相同待机功耗下，读取电流（I）增加了18.7%，位线写入余量（BWRM）增加了12.5%。通过电路仿真，案例5模型（PTS掺杂浓度：5.1×10¹⁸ cm⁻³，带有BO）是实现最佳器件和电路性能的最佳条件。这些观察结果证实，在mNS - FET中应用PTS和底部隔离可用于使此类晶体管的卓越特性转化为高性能集成电路。
