Xu Peipei, Liang Jiakun, Li Hong, Liu Fengbin, Tie Jun, Jiao Zhiwei, Luo Jing, Lu Jing
College of Mechanical and Material Engineering, North China University of Technology Beijing 100144 P. R. China
Beijing Research Institute of Automation for Machinery Industry Beijing P. R. China.
RSC Adv. 2020 Apr 22;10(27):16071-16078. doi: 10.1039/d0ra02265a. eCollection 2020 Apr 21.
Exploring the device performance limits is meaningful for guiding practical device fabrication. We propose archetype tunneling field effect transistors (TFETs) with negative capacitance (NC) and use the rigorous quantum transport simulation to explore the device performance limits of the TFETs based on monolayer (ML) GeSe and GeTe along with their NC counterparts. With the ferroelectric dielectric acting as a negative capacitance material, the device performances of both the ML GeSe and GeTe NCTFETs outperform their TFET counterparts, particularly for the on-state current ( ). of the optimal ML GeSe and GeTe TFETs fulfills the demands of the International Technology Roadmap for Semiconductors (ITRS 2015 version) for low power (LP) and high performance (HP) devices, at the "6/5" node range, while with the aid of 80 nm and 50 nm thickness of ferroelectric SrBiNbO, both their NC counterparts extend the fulfillments at the "4/3" node range.
探索器件性能极限对于指导实际器件制造具有重要意义。我们提出了具有负电容（NC）的原型隧穿场效应晶体管（TFET），并使用严格的量子输运模拟来探索基于单层（ML）GeSe和GeTe的TFET及其具有负电容的对应器件的性能极限。由于铁电介质作为负电容材料，ML GeSe和GeTe负电容隧穿场效应晶体管（NCTFET）的器件性能均优于其对应的TFET，特别是对于导通电流（ ）。最佳的ML GeSe和GeTe TFET的 满足了国际半导体技术路线图（ITRS 2015版）对低功耗（LP）和高性能（HP）器件在“6/5”节点范围内的要求，而借助80 nm和50 nm厚度的铁电体SrBiNbO，它们具有负电容的对应器件在“4/3”节点范围内都扩展了满足要求的范围。
