Department of Electrical and Computer Engineering, University of California, Santa Barbara, California 93106, USA.
Department of Materials Science and Nanoengineering, Rice University, Houston, Texas 77005, USA.
Nature. 2015 Oct 1;526(7571):91-5. doi: 10.1038/nature15387.
The fast growth of information technology has been sustained by continuous scaling down of the silicon-based metal-oxide field-effect transistor. However, such technology faces two major challenges to further scaling. First, the device electrostatics (the ability of the transistor's gate electrode to control its channel potential) are degraded when the channel length is decreased, using conventional bulk materials such as silicon as the channel. Recently, two-dimensional semiconducting materials have emerged as promising candidates to replace silicon, as they can maintain excellent device electrostatics even at much reduced channel lengths. The second, more severe, challenge is that the supply voltage can no longer be scaled down by the same factor as the transistor dimensions because of the fundamental thermionic limitation of the steepness of turn-on characteristics, or subthreshold swing. To enable scaling to continue without a power penalty, a different transistor mechanism is required to obtain subthermionic subthreshold swing, such as band-to-band tunnelling. Here we demonstrate band-to-band tunnel field-effect transistors (tunnel-FETs), based on a two-dimensional semiconductor, that exhibit steep turn-on; subthreshold swing is a minimum of 3.9 millivolts per decade and an average of 31.1 millivolts per decade for four decades of drain current at room temperature. By using highly doped germanium as the source and atomically thin molybdenum disulfide as the channel, a vertical heterostructure is built with excellent electrostatics, a strain-free heterointerface, a low tunnelling barrier, and a large tunnelling area. Our atomically thin and layered semiconducting-channel tunnel-FET (ATLAS-TFET) is the only planar architecture tunnel-FET to achieve subthermionic subthreshold swing over four decades of drain current, as recommended in ref. 17, and is also the only tunnel-FET (in any architecture) to achieve this at a low power-supply voltage of 0.1 volts. Our device is at present the thinnest-channel subthermionic transistor, and has the potential to open up new avenues for ultra-dense and low-power integrated circuits, as well as for ultra-sensitive biosensors and gas sensors.
信息技术的快速发展得益于硅基金属氧化物场效应晶体管的不断缩小。然而，这种技术在进一步缩小尺寸方面面临着两个主要挑战。首先，当使用传统的体硅等作为沟道材料时，器件的静电（晶体管栅电极控制其沟道势的能力）会随着沟道长度的减小而降低。最近，二维半导体材料作为硅的替代品而崭露头角，因为它们即使在沟道长度大大减小的情况下也能保持出色的器件静电。其次，更严峻的挑战是，由于开启特性（或亚阈值摆幅）陡峭的热离子限制，供应电压不能再像晶体管尺寸那样按相同的比例缩小。为了在不增加功耗的情况下继续缩小尺寸，需要一种不同的晶体管机制来获得亚热离子亚阈值摆幅，例如带间隧穿。在这里，我们展示了基于二维半导体的带间隧穿场效应晶体管（隧穿 FET），它具有陡峭的开启特性；亚阈值摆幅最低为 3.9 毫伏每 decade，在室温下四个 decade 的漏电流范围内平均为 31.1 毫伏每 decade。通过使用高掺杂的锗作为源极和原子层厚的二硫化钼作为沟道，我们构建了具有出色静电学性能、无应变异质界面、低隧穿势垒和大隧穿面积的垂直异质结构。我们的原子层厚和分层半导体沟道隧穿 FET（ATLAS-TFET）是唯一一种在四个 decade 的漏电流范围内实现亚热离子亚阈值摆幅的平面架构隧穿 FET，符合参考文献 17 的建议，也是唯一一种在 0.1 伏低电源电压下实现这一目标的隧穿 FET（在任何架构中）。我们的器件目前是沟道最薄的亚热离子晶体管，有可能为超密集和低功耗集成电路以及超灵敏生物传感器和气体传感器开辟新途径。
