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基于晶圆级二维半导体的传输晶体管逻辑电路。

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

作者信息

Wang Xinyu, Chen Xinyu, Ma Jingyi, Gou Saifei, Guo Xiaojiao, Tong Ling, Zhu Junqiang, Xia Yin, Wang Die, Sheng Chuming, Chen Honglei, Sun Zhengzong, Ma Shunli, Riaud Antoine, Xu Zihan, Cong Chunxiao, Qiu Zhijun, Zhou Peng, Xie Yufeng, Bian Lifeng, Bao Wenzhong

机构信息

State Key Laboratory of ASIC and System, School of Microelectronics, Zhangjiang Fudan International Innovation Center, Fudan University, Shanghai, 200433, China.

School of Information Science and Engineering, Fudan University, Shanghai, 200433, China.

出版信息

Adv Mater. 2022 Dec;34(48):e2202472. doi: 10.1002/adma.202202472. Epub 2022 Jul 10.

DOI:10.1002/adma.202202472
PMID:35728050
Abstract

2D semiconductors, such as molybdenum disulfide (MoS ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

摘要

二维半导体,如二硫化钼(MoS ),在构建用于未来柔性和节能电子产品的先进单片集成电路(IC)方面引起了极大关注。然而,基于二维材料的大规模集成电路的发展仍处于早期阶段,主要是由于单个器件的不均匀性以及对器件和电路级优化的研究较少。在此,成功合成了4英寸高质量单层MoS薄膜,然后用于制造具有晶圆级均匀性的顶栅(TG)MoS场效应晶体管。对一些基本电路,如静态随机存取存储器和环形振荡器进行了研究。然后采用基于伪NMOS的传输晶体管逻辑配置来设计更复杂的MoS逻辑电路,并成功制造出具有经过测试的适当逻辑功能的电路。这些初步的集成工作展示了晶圆级二维半导体在复杂集成电路中应用的广阔前景。

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引用本文的文献

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Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.通过范德华层压实现整体式三维层层集成。
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