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通过反铁电/铁电(ZrO/HZO)双层异质结构和高压退火在准同型相界附近实现高κ(约59)和低等效氧化层厚度(约3.8 Å)的新方法。

Novel Approach to High κ (∼59) and Low EOT (∼3.8 Å) near the Morphotrophic Phase Boundary with AFE/FE (ZrO/HZO) Bilayer Heterostructures and High-Pressure Annealing.

作者信息

Gaddam Venkateswarlu, Kim Giuk, Kim Taeho, Jung Minhyun, Kim Chaeheon, Jeon Sanghun

机构信息

School of Electrical Engineering, Korea Advanced Institute of Science & Technology, Daejeon 34141, Korea.

出版信息

ACS Appl Mater Interfaces. 2022 Sep 28;14(38):43463-43473. doi: 10.1021/acsami.2c08691. Epub 2022 Sep 15.

DOI:10.1021/acsami.2c08691
PMID:36108249
Abstract

We present herewith a novel approach of equally thick AFE/FE (ZrO/HZO) bilayer stack heterostructure films for achieving an equivalent oxide thickness (EOT) of 4.1 Å with a dielectric constant (κ) of 56 in complementary metal-oxide semiconductor (CMOS) compatible metal-ferroelectric-metal (MFM) capacitors using a high-pressure annealing (HPA) technique. The low EOT and high κ values were achieved by careful optimization of AFE/FE film thicknesses and HPA conditions near the morphotropic phase boundary (MPB) after field cycling effects. Stable leakage current density ( < 10 A/cm at ±0.8 V) was found at 3/3 nm bilayer stack films (κ = 56 and EOT = 4.1 Å) measured at room temperature. In comparison with previous work, our remarkable achievement stems from the interfacial coupling between FE and AFE films as well as a high-quality crystalline structure formed by HPA. Kinetically stabilized hafnia films result in a small grain size in bilayer films, leading to reducing the leakage current density. Further, a higher κ value of 59 and lower EOT of 3.4 Å were found at 333 K. However, stable leakage current density was found at 273 K with a high κ value of 53 and EOT of 3.85 Å with < 10 A/cm. This is the lowest recorded EOT employing hafnia and TiN electrodes that are compatible with CMOS, and it has important implications for future dynamic random access memory (DRAM) technology.

摘要

我们在此展示了一种新颖的等厚反铁电/铁电(ZrO/HZO)双层堆叠异质结构薄膜的方法,该方法通过高压退火(HPA)技术,在互补金属氧化物半导体(CMOS)兼容的金属 - 铁电 - 金属(MFM)电容器中实现了等效氧化物厚度(EOT)为4.1 Å,介电常数(κ)为56。通过在场循环效应后仔细优化反铁电/铁电薄膜厚度和接近准同型相界(MPB)的HPA条件,实现了低EOT和高κ值。在室温下测量的3/3 nm双层堆叠薄膜(κ = 56,EOT = 4.1 Å)中发现了稳定的漏电流密度(±0.8 V时<10 A/cm²)。与先前的工作相比,我们的显著成就源于铁电和反铁电薄膜之间的界面耦合以及由HPA形成的高质量晶体结构。动力学稳定的氧化铪薄膜导致双层薄膜中的晶粒尺寸较小,从而降低了漏电流密度。此外,在333 K时发现κ值更高为59,EOT更低为3.4 Å。然而,在273 K时发现了稳定的漏电流密度,κ值为53,EOT为3.85 Å,漏电流密度<10 A/cm²。这是使用与CMOS兼容的氧化铪和氮化钛电极记录的最低EOT,对未来的动态随机存取存储器(DRAM)技术具有重要意义。

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