Department of Electronic Engineering, Xi'an University of Technology, No. 5 Jinhua South Road, Xi'an 710054, China.
Sensors (Basel). 2023 Jan 4;23(2):595. doi: 10.3390/s23020595.
The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.
由于传统单斜率和串行两步模数转换器 (ADC) 的速度限制，高帧率 CMOS 图像传感器 (CIS) 的应用要求尚未得到满足。本文提出了一种用于 CIS 的高速全差分两步 ADC 设计方法。该方法基于差分斜坡和时间数字转换器 (TDC) 技术。形成了一种不同于串行转换的并行转换模式，并由于差分斜坡的存在保证了系统的鲁棒性。针对传统 TDC 技术与单斜率 ADC 的不一致性，提出了一种基于电平编码的 TDC 技术。该技术在模数转换的最后一个时钟周期实现 TDC，并在另一个电平实现两步转换过程。本文基于 55nm1P4MCMOS 实验平台，提出了一种完整的电路设计、布局设计和对所提出设计方法的测试验证。在模拟电压为 3.3V、数字电压为 1.2V、时钟频率为 100MHz、动态输入范围为 1.6V 的设计环境下，该设计为 12 位 ADC，转换时间为 480ns，列级功耗为 62μW，差分非线性 (DNL) 为+0.6/-0.6LSB，积分非线性 (INL) 为+1.2/-1.4LSB。此外，它还实现了 70.08dB 的信噪失真比 (SNDR)。该设计为大面阵提供了高帧率，与现有的先进单斜率 ADC 相比，其转换速度提高了 52%以上。为高帧频 CIS 的实现提供了有效的解决方案。
