用于硅量子器件的铝栅替代方案：缺陷与应变。
Alternatives to aluminum gates for silicon quantum devices: defects and strain.
作者信息
Stein Ryan M, Barcikowski Z S, Pookpanratana S J, Pomeroy J M, Stewart M D
机构信息
Department of Materials Science and Engineering, University of Maryland, College Park, Maryland 20742, USA.
National Institute of Standards and Technology, Gaithersburg, MD, 20899, USA.
出版信息
J Appl Phys. 2021;130(11). doi: 10.1063/5.0036520.
Gate-defined quantum dots (QD) benefit from the use of small grain size metals for gate materials because it aids in shrinking the device dimensions. However, it is not clear what differences arise with respect to process-induced defect densities and inhomogeneous strain. Here, we present measurements of fixed charge, , interface trap density, , the intrinsic film stress, , and the coefficient of thermal expansion, as a function of forming gas anneal temperature for Al, Ti/Pd, and Ti/Pt gates. We show is minimal at an anneal temperature of 350 °C for all materials but Ti/Pd and Ti/Pt have higher and compared to Al. In addition, and increase with anneal temperature for all three metals with larger than the bulk value. These results indicate that there is a tradeoff between minimizing defects and minimizing the impact of strain in quantum device fabrication.
栅极定义的量子点（QD）受益于使用小晶粒尺寸的金属作为栅极材料，因为这有助于缩小器件尺寸。然而，尚不清楚在工艺诱导的缺陷密度和不均匀应变方面会出现哪些差异。在这里，我们给出了固定电荷、界面陷阱密度、本征薄膜应力和热膨胀系数随Al、Ti/Pd和Ti/Pt栅极的形成气体退火温度变化的测量结果。我们表明，对于所有材料，在350°C的退火温度下固定电荷最小，但与Al相比，Ti/Pd和Ti/Pt具有更高的界面陷阱密度和本征薄膜应力。此外，对于所有三种金属，界面陷阱密度和本征薄膜应力都随退火温度增加，且大于体值。这些结果表明，在量子器件制造中，在最小化缺陷和最小化应变影响之间存在权衡。
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