Bobinac Josip, Reiter Tobias, Piso Julius, Klemenschits Xaver, Baumgartner Oskar, Stanojevic Zlatan, Strof Georg, Karner Markus, Filipovic Lado
Christian Doppler Laboratory for Multi-Scale Process Modeling of Semiconductor Devices and Sensors at the Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Vienna, Austria.
Institute for Microelectronics, TU Wien, Gußhausstraße 27-29/E360, 1040 Vienna, Austria.
Micromachines (Basel). 2023 Mar 16;14(3):665. doi: 10.3390/mi14030665.
It is becoming quite evident that, when it comes to the further scaling of advanced node transistors, increasing the flash memory storage capacity, and enabling the on-chip integration of multiple functionalities, "there's plenty of room at the top". The fabrication of vertical, three-dimensional features as enablers of these advanced technologies in semiconductor devices is commonly achieved using plasma etching. Of the available plasma chemistries, SF/O is one of the most frequently applied. Therefore, having a predictive model for this process is indispensable in the design cycle of semiconductor devices. In this work, we implement a physical SF/O plasma etching model which is based on Langmuir adsorption and is calibrated and validated to published equipment parameters. The model is implemented in a broadly applicable in-house process simulator ViennaPS, which includes Monte Carlo ray tracing and a level set-based surface description. We then use the model to study the impact of the mask geometry on the feature profile, when etching through circular and rectangular mask openings. The resulting dimensions of a cylindrical hole or trench can vary greatly due to variations in mask properties, such as its etch rate, taper angle, faceting, and thickness. The peak depth for both the etched cylindrical hole and trench occurs when the mask is tapered at about 0.5°, and this peak shifts towards higher angles in the case of high passivation effects during the etch. The minimum bowing occurs at the peak depth, and it increases with an increasing taper angle. For thin-mask faceting, it is observed that the maximum depth increases with an increasing taper angle, without a significant variation between thin masks. Bowing is observed to be at a maximum when the mask taper angle is between 15° and 20°. Finally, the mask etch rate variation, describing the etching of different mask materials, shows that, when a significant portion of the mask is etched away, there is a notable increase in vertical etching and a decrease in bowing. Ultimately, the implemented model and framework are useful for providing a guideline for mask design rules.
越来越明显的是，在先进节点晶体管的进一步缩放、增加闪存存储容量以及实现多种功能的片上集成方面，“高端仍有很大空间”。在半导体器件中制造垂直的三维特征以实现这些先进技术，通常采用等离子体蚀刻。在可用的等离子体化学物质中，SF/O是最常用的之一。因此，在半导体器件的设计周期中，拥有该工艺的预测模型是必不可少的。在这项工作中，我们实现了一个基于朗缪尔吸附的物理SF/O等离子体蚀刻模型，并根据已发表的设备参数进行了校准和验证。该模型在广泛适用的内部工艺模拟器ViennaPS中实现，该模拟器包括蒙特卡罗射线追踪和基于水平集的表面描述。然后，我们使用该模型研究在蚀刻圆形和矩形掩膜开口时掩膜几何形状对特征轮廓的影响。由于掩膜特性的变化，如蚀刻速率、锥角、刻面和厚度，蚀刻后的圆柱形孔或沟槽的最终尺寸可能会有很大差异。蚀刻后的圆柱形孔和沟槽的峰值深度出现在掩膜锥角约为0.5°时，在蚀刻过程中钝化效应较强的情况下，该峰值会向更大角度移动。最小弯曲出现在峰值深度处，并且随着锥角的增加而增加。对于薄掩膜刻面，观察到最大深度随着锥角的增加而增加，薄掩膜之间没有显著差异。当掩膜锥角在15°至20°之间时，弯曲最大。最后，描述不同掩膜材料蚀刻情况的掩膜蚀刻速率变化表明，当大部分掩膜被蚀刻掉时，垂直蚀刻会显著增加，弯曲会减小。最终，所实现的模型和框架有助于为掩膜设计规则提供指导。
