Liu Enxu, Li Junjie, Zhou Na, Chen Rui, Shao Hua, Gao Jianfeng, Zhang Qingzhu, Kong Zhenzhen, Lin Hongxiao, Zhang Chenchen, Lai Panpan, Yang Chaoran, Liu Yang, Wang Guilei, Zhao Chao, Yang Tao, Yin Huaxiang, Li Junfeng, Luo Jun, Wang Wenwu
Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing 100029, China.
Microelectronics Institute, University of Chinese Academy of Sciences, Beijing 100049, China.
Nanomaterials (Basel). 2023 Jul 21;13(14):2127. doi: 10.3390/nano13142127.
Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-spacer cavity etching and channel release both require selective etching of SiGe. Increasing the number of channel-stacking layers is an effective way to improve device current-driving capability and storage density. Previous work investigated ICP selective etching of a three-cycle SiGe/Si multilayer structure and the related etching effects. This study focuses on the dry etching of a 15-cycle SiGe/Si multilayer structure and the associated etching effects, using simulation and experimentation. The simulation predicts the random effect of lateral etching depth and the asymmetric effect of silicon nanosheet damage on the edge, both of which are verified by experiments. Furthermore, the study experimentally investigates the influence and mechanism of pressure, power, and other parameters on the etching results. Research on these etching effects and mechanisms will provide important points of reference for the dry selective etching of SiGe in GAA structures.
全栅（GAA）结构对于未来的逻辑器件和3D-DRAM至关重要。内间隔层腔蚀刻和沟道释放都需要对SiGe进行选择性蚀刻。增加沟道堆叠层数是提高器件电流驱动能力和存储密度的有效方法。先前的工作研究了三周期SiGe/Si多层结构的电感耦合等离子体（ICP）选择性蚀刻及相关蚀刻效果。本研究聚焦于使用模拟和实验对15周期SiGe/Si多层结构进行干法蚀刻及相关蚀刻效果。模拟预测了横向蚀刻深度的随机效应以及硅纳米片边缘损伤的不对称效应，这两者均通过实验得到验证。此外，该研究通过实验探究了压力、功率和其他参数对蚀刻结果的影响及机制。对这些蚀刻效果和机制的研究将为GAA结构中SiGe的干法选择性蚀刻提供重要参考依据。
