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一种用于制造全栅晶体管的新型硅纳米片沟道释放工艺及其机理研究。

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation.

作者信息

Sun Xin, Wang Dawei, Qian Lewen, Liu Tao, Yang Jingwen, Chen Kun, Wang Luyu, Huang Ziqiang, Xu Min, Wang Chen, Wu Chunlei, Xu Saisheng, Zhang David Wei

机构信息

State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China.

Shanghai Integrated Circuit Manufacturing Innovation Center Co., Ltd., Shanghai 201202, China.

出版信息

Nanomaterials (Basel). 2023 Jan 27;13(3):504. doi: 10.3390/nano13030504.

DOI:10.3390/nano13030504
PMID:36770465
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC9920338/
Abstract

The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for SiGe versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

摘要

研究了源极/漏极压应力在沟道释放过程中对堆叠硅纳米片(NS)机械稳定性的影响。通过技术计算机辅助设计(TCAD)模拟,在沟道释放过程中,纳米片在堆叠方向上的应力先增加后减小。有限元模拟表明,该应力导致纳米片发生严重变形,实验也证实了这一点。本研究提出了一种新颖的沟道释放工艺,该工艺利用多步蚀刻来去除牺牲SiGe层,而不是传统的单步蚀刻。通过逐步释放纳米片上SiGe层的应力,显著降低了蚀刻最后一步前后堆叠方向上的应力差,从而实现了等间距堆叠纳米片。此外,在多步蚀刻过程中引入了无等离子体氧化处理,以实现SiGe与Si的168:1的优异选择性。所提出的新工艺能够在几乎没有硅损失的情况下实现30纳米至80纳米多种宽度的纳米片沟道释放,释放了全栅(GAA)技术在数字、模拟和射频(RF)电路应用中的全部潜力。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/9e26af7a73ab/nanomaterials-13-00504-g006.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/0a477894d4bc/nanomaterials-13-00504-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/e7ba52249b8e/nanomaterials-13-00504-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/5d15e5a93cd1/nanomaterials-13-00504-g003.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/6714b4b8b447/nanomaterials-13-00504-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/6466b1ed648e/nanomaterials-13-00504-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/9e26af7a73ab/nanomaterials-13-00504-g006.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/0a477894d4bc/nanomaterials-13-00504-g001.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/e7ba52249b8e/nanomaterials-13-00504-g002.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/5d15e5a93cd1/nanomaterials-13-00504-g003.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/6714b4b8b447/nanomaterials-13-00504-g004.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/6466b1ed648e/nanomaterials-13-00504-g005.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/b3ab/9920338/9e26af7a73ab/nanomaterials-13-00504-g006.jpg

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本文引用的文献

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Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors.环绕栅纳米晶体管工艺中氮化硅内间隔层形成的研究
Nanomaterials (Basel). 2020 Apr 20;10(4):793. doi: 10.3390/nano10040793.
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Low-temperature in situ large strain plasticity of ceramic SiC nanowires and its atomic-scale mechanism.
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Nanomaterials (Basel). 2023 Jul 21;13(14):2127. doi: 10.3390/nano13142127.
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