Wu Feitong, Guo Xuan, Jia Hanbo, Wu Xiuheng, Li Zeyu, He Ben, Wu Danyu, Liu Xinyu
Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China.
University of Chinese Academy of Sciences, Beijing 100049, China.
Micromachines (Basel). 2023 Jun 24;14(7):1291. doi: 10.3390/mi14071291.
This paper presents a single-channel 12-bit, 2 GS/s pipelined analog-to-digital converter (ADC) for wideband sampling receivers. The design adopts a novel source follower input buffer with multiple feedback loops to improve sample linearity and extend bandwidth. Additionally, an improved two stages charge pump amplifier topology is introduced, which doubles the Gain Bandwidth Product (GBW) without consuming additional power. To address the back-end ADC and background calibration, a multi-level dither strategy is employed, utilizing a new high-speed and low-cost uniform distribution pseudorandom code generator. The prototype ADC fabricated in 40 nm CMOS process achieves 68.24 dB SFDR up to Nyquist frequency with a sampling rate of 2 GS/s. Measurement results demonstrate a bandwidth exceeding 5 GHz, resulting in a Schreier FOMs of 152.4 dB.
本文介绍了一款用于宽带采样接收器的单通道12位、2 GS/s流水线式模数转换器（ADC）。该设计采用了一种带有多个反馈回路的新型源极跟随器输入缓冲器，以提高采样线性度并扩展带宽。此外，引入了一种改进的两级电荷泵放大器拓扑结构，在不消耗额外功率的情况下使增益带宽积（GBW）翻倍。为了解决后端ADC和背景校准问题，采用了一种多级抖动策略，利用一种新型高速低成本均匀分布伪随机码发生器。采用40 nm CMOS工艺制造的ADC原型在2 GS/s采样率下，直至奈奎斯特频率可实现68.24 dB的无杂散动态范围（SFDR）。测量结果表明带宽超过5 GHz，得到的施赖尔优值为152.4 dB。
