Klimov Paul V, Bengtsson Andreas, Quintana Chris, Bourassa Alexandre, Hong Sabrina, Dunsworth Andrew, Satzinger Kevin J, Livingston William P, Sivak Volodymyr, Niu Murphy Yuezhen, Andersen Trond I, Zhang Yaxing, Chik Desmond, Chen Zijun, Neill Charles, Erickson Catherine, Grajales Dau Alejandro, Megrant Anthony, Roushan Pedram, Korotkov Alexander N, Kelly Julian, Smelyanskiy Vadim, Chen Yu, Neven Hartmut
Google AI, Mountain View, CA, USA.
Department of Electrical and Computer Engineering, University of California, Riverside, CA, USA.
Nat Commun. 2024 Mar 18;15(1):2442. doi: 10.1038/s41467-024-46623-y.
A foundational assumption of quantum error correction theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance. Two major challenges that could become fundamental roadblocks are manufacturing high-performance quantum hardware and engineering a control system that can reach its performance limits. The control challenge of scaling quantum gates from small to large processors without degrading performance often maps to non-convex, high-constraint, and time-dynamic control optimization over an exponentially expanding configuration space. Here we report on a control optimization strategy that can scalably overcome the complexity of such problems. We demonstrate it by choreographing the frequency trajectories of 68 frequency-tunable superconducting qubits to execute single- and two-qubit gates while mitigating computational errors. When combined with a comprehensive model of physical errors across our processor, the strategy suppresses physical error rates by ~3.7× compared with the case of no optimization. Furthermore, it is projected to achieve a similar performance advantage on a distance-23 surface code logical qubit with 1057 physical qubits. Our control optimization strategy solves a generic scaling challenge in a way that can be adapted to a variety of quantum operations, algorithms, and computing architectures.
量子纠错理论的一个基本假设是，量子门可以扩展到大型处理器，而不会超过容错的误差阈值。可能成为基本障碍的两个主要挑战是制造高性能量子硬件以及设计一个能够达到其性能极限的控制系统。在不降低性能的情况下将量子门从小型处理器扩展到大型处理器的控制挑战，通常映射到在指数级扩展的配置空间上进行非凸、高约束和时间动态的控制优化。在此，我们报告一种能够可扩展地克服此类问题复杂性的控制优化策略。我们通过编排68个频率可调谐超导量子比特的频率轨迹来执行单比特和双比特门操作，同时减轻计算误差，从而证明了这一策略。当与我们处理器上的物理误差综合模型相结合时，与未进行优化的情况相比，该策略将物理错误率抑制了约3.7倍。此外，预计在具有1057个物理量子比特的距离-23表面码逻辑量子比特上也能实现类似的性能优势。我们的控制优化策略以一种可适应各种量子操作、算法和计算架构的方式解决了一个通用的扩展挑战。
