Guan He, Li Jiaying, Chen Yangchao, Tang Yongchuan, Li Yunshuo
School of Microelectronics, Northwestern Polytechnical University, Xi'an 710072, China.
Chongqing Innovation Center, Northwestern Polytechnical University, Chongqing 401135, China.
Micromachines (Basel). 2024 Sep 19;15(9):1163. doi: 10.3390/mi15091163.
On-chip electrostatic discharge (ESD) protection poses a challenge in the chip fabrication process. In this study, a novel electric fuse (E-fuse) device featuring a simple structure of Ni metal on a SiO dielectric for ESD protection was proposed, and the physical mechanism of its operation was investigated in detail. Experimental evaluations, utilizing transmission line pulse (TLP) testing and fusing performance analyses, reveal that the E-fuse, constructed with a Ni metal layer measuring 5 μm in width, 100 μm in length, and 5 nm in thickness, achieved a significant ESD protection voltage of 251 V () and demonstrates low-voltage fusing at a bias voltage of 7 V. Compared to traditional ESD protection devices, the E-fuse boasts a smaller size and removability. To assess fusing performance, devices of varying sizes were tested using a fusing lifetime model. This study supports both theoretical and empirical evidence, enabling the adoption of cost-effective, straightforward E-fuse devices for ESD protection.
芯片上的静电放电（ESD）保护在芯片制造过程中是一项挑战。在本研究中，提出了一种新型电熔丝（E-fuse）器件，其具有用于ESD保护的SiO电介质上的简单Ni金属结构，并详细研究了其工作的物理机制。利用传输线脉冲（TLP）测试和熔断性能分析进行的实验评估表明，由宽度为5μm、长度为100μm、厚度为5nm的Ni金属层构成的E-fuse实现了251V（）的显著ESD保护电压，并在7V的偏置电压下表现出低电压熔断。与传统的ESD保护器件相比，E-fuse具有更小的尺寸和可移除性。为了评估熔断性能，使用熔断寿命模型对不同尺寸的器件进行了测试。本研究提供了理论和实证依据，使得能够采用具有成本效益、简单的E-fuse器件进行ESD保护。
