Venkatakrishnarao Dasari, Mishra Abhishek, Tarn Yaoju, Bosman Michel, Lee Rainer, Das Sarthak, Mukherjee Subhrajit, Talha-Dean Teymour, Zhang Yiyu, Teo Siew Lang, Chai Jianwei, Bussolotti Fabio, Goh Kuan Eng Johnson, Lau Chit Siong
Institute of Materials Research and Engineering (IMRE), Agency for Science Technology and Research (A*STAR), 2 Fusionopolis Way, Innovis #08-03, Singapore 138634, Republic of Singapore.
Department of Chemistry, IIT Bombay, Powai, Mumbai 400076, India.
ACS Nano. 2024 Oct 1;18(39):26911-26919. doi: 10.1021/acsnano.4c08554. Epub 2024 Sep 18.
Two-dimensional van der Waals semiconductors are promising for future nanoelectronics. However, integrating high-k gate dielectrics for device applications is challenging as the inert van der Waals material surfaces hinder uniform dielectric growth. Here, we report a liquid metal oxide-assisted approach to integrate ultrathin, high-k HfO dielectric on 2D semiconductors with atomically smooth interfaces. Using this approach, we fabricated 2D WS top-gated transistors with subthreshold swings down to 74.5 mV/dec, gate leakage current density below 10 A/cm, and negligible hysteresis. We further demonstrate a one-step van der Waals integration of contacts and dielectrics on graphene. This can offer a scalable approach toward integrating entire prefabricated device stack arrays with 2D materials. Our work provides a scalable solution to address the crucial dielectric engineering challenge for 2D semiconductor-based electronics.
二维范德华半导体在未来纳米电子学领域颇具前景。然而,由于惰性的范德华材料表面阻碍了均匀介电层的生长,将高k栅极电介质集成到器件应用中具有挑战性。在此,我们报告了一种液态金属氧化物辅助方法,可在二维半导体上集成具有原子级光滑界面的超薄、高k HfO₂电介质。使用这种方法,我们制造了二维WS₂顶栅晶体管,其亚阈值摆幅低至74.5 mV/dec,栅极漏电流密度低于10⁻⁶ A/cm²,且滞后现象可忽略不计。我们进一步展示了在石墨烯上一步实现接触和电介质的范德华集成。这可为将整个预制器件堆栈阵列与二维材料集成提供一种可扩展的方法。我们的工作为解决基于二维半导体的电子学关键介电工程挑战提供了一种可扩展的解决方案。