Li Xunyu, Pan Zijin, Hao Weiquan, Miao Runyu, Yue Zijian, Wang Albert
Department of Electrical and Computer Engineering, University of California, Riverside, CA 92521, USA.
Micromachines (Basel). 2025 Apr 21;16(4):488. doi: 10.3390/mi16040488.
The ending of Moore's Law calls for innovations in integrated circuit (IC) technologies and chip designs. Heterogeneous integration (HI) emerges as a pathway towards smart future chips for more Moore time and for beyond-Moore time, featuring systems-on-integrated-chiplets (SoICs) and advanced micro-packaging (μ-packaging). Reliability, particularly with regard to electrostatic charge (ESD) failure, is a major challenge for 3D SoIC chips in μ-packaging, which is an emerging design-for-reliability challenge for future chips. This perspective article articulates that interposer-based ESD protection will be an important potential solution for 3D SoIC chips in μ-packaging against the devastating ESD failure problem.
摩尔定律的终结促使集成电路（IC）技术和芯片设计进行创新。异构集成（HI）应运而生，成为通往智能未来芯片的途径，适用于延长摩尔时代及超越摩尔时代，其特点是集成小芯片系统（SoIC）和先进的微封装（μ封装）。可靠性，尤其是静电电荷（ESD）失效方面的可靠性，是μ封装中3D SoIC芯片面临的一项重大挑战，这是未来芯片在可靠性设计方面新出现的挑战。这篇观点文章阐明，基于中介层的ESD保护将是μ封装中3D SoIC芯片应对极具破坏性的ESD失效问题的一个重要潜在解决方案。
