Palomäki Kalle I, Nurmi Jari
Wireless Research Center, Tampere University, 33720 Tampere, Finland.
Sensors (Basel). 2025 Apr 10;25(8):2403. doi: 10.3390/s25082403.
A common challenge in direct digital frequency synthesizers (DDFSs) is obtaining high memory compression while maintaining good output signal purity. To address this challenge, in this paper, we present a 16-bit, quadrature direct digital frequency synthesizer (DDFS) that utilizes the second-order Taylor series polynomial interpolation in the phase-to-amplitude conversion. In this approach, the sinusoidal signal is divided into multiple segments, and for each segment, related values are stored into a look-up table (LUT). The amplitude values for each segment are calculated using the stored LUT values and the second-order Taylor series polynomial interpolation. A Python-based model was created to optimize the number of segments, and the resulting design was coded using register-transfer level VHDL. The design is synthesized and implemented on an AMD Artix 7 FPGA, and the implementation results are presented. We show that the proposed design is capable of reaching a very high memory compression ratio of 5178:1. Additionally, the design generates both sine and cosine with high spectral purity utilizing a low number of FPGA resources compared to previous work. With 107 logic slices and 3 DSP slices, the design reaches a spurious-free dynamic range (SFDR) of -102.9 dBc.
直接数字频率合成器（DDFS）中的一个常见挑战是在保持良好输出信号纯度的同时实现高内存压缩。为应对这一挑战，在本文中，我们提出了一种16位正交直接数字频率合成器（DDFS），该合成器在相位到幅度转换中采用二阶泰勒级数多项式插值。在这种方法中，正弦信号被分成多个段，并且对于每个段，相关值被存储到一个查找表（LUT）中。每个段的幅度值使用存储的LUT值和二阶泰勒级数多项式插值来计算。创建了一个基于Python的模型来优化段数，并使用寄存器传输级VHDL对最终设计进行编码。该设计在AMD Artix 7 FPGA上进行综合和实现，并展示了实现结果。我们表明，所提出的设计能够达到5178:1的非常高的内存压缩比。此外，与之前的工作相比，该设计利用少量FPGA资源生成具有高光谱纯度的正弦和余弦信号。该设计使用107个逻辑切片和3个DSP切片，达到了-102.9 dBc的无杂散动态范围（SFDR）。
