Chen Riguang, Chen Ping, Li Kuinian, Liu Hulin
Key Laboratory of Ultra-Fast Photoelectric Diagnostics Technology, Xi'an Institute of Optics and Precision Mechanics of CAS, Xi'an 710119, China.
University of Chinese Academy of Sciences, Beijing 100049, China.
Sensors (Basel). 2025 May 6;25(9):2923. doi: 10.3390/s25092923.
Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring single-cycle dead time and multi-channel expansion capabilities, with an original precision of 30 ps. Combined with jTDC's dynamic caching mechanism using dual-page memory, this work employs a dual-cycle encoding and calibration. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. According to the experimental results, an optimal 3-tap heterogeneous TDL architecture achieves a resolution of 23.220 ps and a typical precision of 17.520 ps, whereas an optimal 4-tap heterogeneous TDL architecture demonstrates a resolution of 17.530 ps and a typical precision of 17.213 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article.
基于现场可编程门阵列（FPGA）实现的时间数字转换器（TDC），因其性价比高、精度高和开发周期短，在高能物理实验、自动驾驶、机器人导航和医学成像等广泛的科学和工程学科中越来越普遍。本文提出了一种用于基于FPGA的TDC的三抽头异构抽头延迟线（TDL）架构，该架构可用于多通道飞行时间测量。该TDC设计基于开源的jTDC，具有单周期死区时间和多通道扩展能力，原始精度为30 ps。结合jTDC使用双页内存的动态缓存机制，这项工作采用了双周期编码和校准。所提出的架构已在赛灵思Artix-7 FPGA上实现。根据实验结果，最优的三抽头异构TDL架构实现了23.220 ps的分辨率和17.520 ps的典型精度，而最优的四抽头异构TDL架构的分辨率为17.530 ps，典型精度为17.213 ps。文章末尾提供了与最近发表的基于FPGA的最先进TDC的比较。
