Mageshwari Narayanan, Sakthivel Periyasamy, Seetharaman Ramasamy
Department of Electronics and Communication Engineering, College of Engineering Guindy Campus, Anna University, Chennai, 600025, India.
Sci Rep. 2025 May 28;15(1):18764. doi: 10.1038/s41598-025-04002-7.
With the evolving modern-day communication applications, there is a need for an effectively improved performance in multiplication operations. In today's scenario, multiplication operations based on Vedic mathematics have the primary advantage that the propagation delay due to a larger number of input bits is reduced compared to other multipliers. Higher speed Vedic multipliers, especially based on Urdhva Tiryagbhyam (vertically and crosswise) sutra, perform multiplication in a way that allows parallel processing with reduced delay. Compared to conventional multipliers like array or Booth multipliers, Vedic multipliers may have less area and power, depending on implementation. In this work, a high-speed 64-bit reversible Vedic multiplier is proposed using five different adders, namely reversible ripple carry adder (RRCA), reversible carry look-ahead adder (RCLA), reversible carry save adder (RCSA), reversible carry bypass or carry skip adder (RCSKA)adder, and reversible carry select adder (RCSLA). The main objective of utilizing logic optimization in reversible logic along with the Vedic multiplier is to develop low-power and high-speed digital circuits. The proposed n-bit reversible Vedic multiplier is simulated using Xilinx Vivado 2019.1 and synthesized in the Cadence EDA tool in 90 nm and 180 nm technology. The proposed 16-bit reversible Vedic multipliers using the proposed 2-bit reversible multiplier provide 24% and 28% less propagation delay than the related work Mohana Priya et al. (Int. J. Syst. Assur. Eng. Manag. 14:829-835, 2023). The 16-bit reversible Vedic multiplier proposed using the existing 2-bit reversible multiplier provides 53% lesser area and 52% less power than the reference work Deepa et al. (Sadhana 44:197, 2019). Similarly, the proposed 32-bit reversible Vedic multiplier offers 15% better delay than (Padma et al. in Comput. Electr. Eng. 92:107178, 2021), 53% less area, and 45% less power than (Deepa et al.in Sadhana 44:197, 2019). Using the proposed reversible Vedic multiplier, a 32-bit MAC unit is designed and implemented using Cadence 90 nm and 180 nm technology. Thus, the proposed work can be applied to the most promising fields such as Microprocessors to design MAC units, to find the convolution in Digital signal processing applications, Communication, RF sensing applications, etc.
随着现代通信应用的不断发展，乘法运算的性能需要得到有效提升。在当今的情况下，基于吠陀数学的乘法运算具有主要优势，即与其他乘法器相比，由于输入比特数较多而导致的传播延迟得以减少。更高速度的吠陀乘法器，尤其是基于“Urdhva Tiryagbhyam”（纵向和交叉）经文的乘法器，其执行乘法的方式允许进行并行处理且延迟降低。与诸如阵列乘法器或布斯乘法器等传统乘法器相比，吠陀乘法器根据实现方式可能具有更小的面积和功耗。在这项工作中，提出了一种使用五种不同加法器的高速64位可逆吠陀乘法器，即可逆 ripple 进位加法器（RRCA）、可逆先行进位加法器（RCLA）、可逆进位保存加法器（RCSA）、可逆进位旁路或进位跳跃加法器（RCSKA）以及可逆进位选择加法器（RCSLA）。在可逆逻辑中利用逻辑优化以及吠陀乘法器的主要目标是开发低功耗和高速的数字电路。所提出的n位可逆吠陀乘法器使用Xilinx Vivado 2019.1进行了仿真，并在Cadence EDA工具中采用90纳米和180纳米技术进行了综合。与相关工作Mohana Priya等人（《国际系统保障工程与管理杂志》14:829 - 835，2023年）相比，使用所提出的2位可逆乘法器的16位可逆吠陀乘法器的传播延迟减少了24%和28%。与参考工作Deepa等人（《Sadhana》44:197，2019年）相比，使用现有2位可逆乘法器提出的16位可逆吠陀乘法器的面积减少了53%，功耗减少了52%。同样，所提出的32位可逆吠陀乘法器的延迟比（Padma等人，《计算机与电子工程》92:107178，2021年）提高了15%，面积比（Deepa等人，《Sadhana》44:197，2019年）减少了53%，功耗减少了45%。使用所提出的可逆吠陀乘法器，采用Cadence 90纳米和180纳米技术设计并实现了一个32位乘法累加（MAC）单元。因此，所提出的工作可以应用于最有前景的领域，如用于设计MAC单元的微处理器、在数字信号处理应用中进行卷积运算、通信、射频传感应用等。
