Liu Yan, Hao Mingyu, Xu Hui, Gao Xiang, Zheng Haiyong
College of Electronic Engineering, Ocean University of China, Qingdao 266404, China.
Sensors (Basel). 2025 Jun 29;25(13):4059. doi: 10.3390/s25134059.
The inherent non-ideal characteristics of circuit components and inter-channel mismatch errors induce nonlinear amplitude and phase distortions in time-interleaved pipelined analog-to-digital converters (TI-pipelined ADCs), significantly degrading system performance. Limited by prior modeling, conventional digital calibration methods only correct partial errors, while machine learning (ML) approaches achieve comprehensive calibration at a high computational cost. This work proposes an ensemble calibration framework that combines polynomial modeling and ML techniques. The ensemble calibration framework employs a two-stage correction: a learned Volterra front-end performs forward mapping to compensate static baseline nonlinear distortions, while a lightweight neural network back-end implements inverse mapping to correct dynamic nonlinear distortions and inter-channel mismatch errors adaptively. Experiments conducted on TI-pipelined ADCs show improvements in both the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR). It is noteworthy that in two ADCs fabricated using 40 nm CMOS technology, the 12-bit, 3000 MS/s silicon-validated four-channel TI-pipelined ADC exhibits SFDR and SNDR improvements from 35.47 dB and 35.35 dB to 79.70 dB and 55.63 dB, respectively, while the 16-bit, 1000 MS/s silicon-validated four-channel TI-pipelined ADC demonstrates an enhancement from 38.62 dB and 40.21 dB to 80.90 dB and 62.43 dB, respectively. Furthermore, a comparison with related studies reveals that our method achieves comprehensive calibration performance for wide-band inputs while substantially reducing computational complexity, requiring only 4.4 K parameters and 8.57 M floating-point operations per second (FLOPs).
电路元件固有的非理想特性和通道间失配误差会在时间交织流水线模数转换器(TI 流水线 ADC)中引起非线性幅度和相位失真,显著降低系统性能。受先前建模的限制,传统数字校准方法只能校正部分误差,而机器学习(ML)方法虽能实现全面校准,但计算成本很高。这项工作提出了一种结合多项式建模和 ML 技术的集成校准框架。该集成校准框架采用两阶段校正:一个经过学习的 Volterra 前端执行正向映射以补偿静态基线非线性失真,而一个轻量级神经网络后端实现反向映射以自适应地校正动态非线性失真和通道间失配误差。在 TI 流水线 ADC 上进行的实验表明,无杂散动态范围(SFDR)和信噪失真比(SNDR)均有所改善。值得注意的是,在采用 40 nm CMOS 技术制造的两款 ADC 中,经过硅验证的 12 位、3000 MS/s 四通道 TI 流水线 ADC 的 SFDR 和 SNDR 分别从 35.47 dB 和 35.35 dB 提高到 79.70 dB 和 55.63 dB,而 16 位、1000 MS/s 四通道 TI 流水线 ADC 则分别从 38.62 dB 和 40.21 dB 提高到 80.90 dB 和 62.43 dB。此外,与相关研究的比较表明,我们的方法在大幅降低计算复杂度的同时,实现了对宽带输入的全面校准性能,每秒仅需 4.4 K 参数和 8.57 M 浮点运算(FLOP)。