The Modeling of a Single-Electron Bipolar Avalanche Transistor in 150 nm CMOS.

This paper addresses the complex behavior of Single-Electron Bipolar Avalanche Transistors (SEBATs) through a comprehensive modeling approach. TCAD simulations were used to analyze the behavior of the device during avalanche pulses triggered by electron injection. The simulations consider the avalanche process and charge flow and include the parasitic capacitances and resistances. A SPICE model is proposed using parameters extracted from the TCAD simulations. Both TCAD and SPICE simulations are validated against experimental results obtained on 150 nm CMOS devices and are employed to provide a clear understanding of the phenomena observed experimentally during SEBAT operation. The impact of parasitic elements on device operation is studied using simulations. This work enables the optimization of SEBAT devices and their integration in circuits for better signal-to-noise ratios, efficiency, and potential applications in sensing and digitizing low-level signals.