Leong P H, Jabri M A
Department of Electrical Engineering, University of Australia, NSW.
Int J Neural Syst. 1993 Dec;4(4):381-94. doi: 10.1142/s0129065793000316.
An analogue neural network VLSI chip designed for low power operation is presented. This chip consists of 84 synapse elements arranged as arrays of size 10 x 6 and 6 x 4 and was fabricated using a standard 1.2 micron double metal single poly CMOS process. The synapses are digitally programmable and static weight storage is provided. The chip has a typical power consumption of tens of microwatts. It has been successfully trained and tested on a range of classification problems including 4-bit parity, character recognition and morphological-based classification of intracardiac electrogram signals.
