Lehmann T
Computational Neural Network Center, Technical University of Denmark, Lyngby.
Int J Neural Syst. 1993 Dec;4(4):351-8. doi: 10.1142/s0129065793000298.
In this paper, an analogue, cascadable, CMOS chip set for artificial neural networks is presented. The chip set (a synapse chip and a neuron chip) offer on-chip back-propagation learning in a fully parallel, layered, feedforward network of arbitrary size and topology. The learning scheme is implemented with no extra circuits at the synapse sites (compared to the system without the learning scheme) and extra circuits of a complexity only about the same as the neurons at the neuron sites. Also, no additional wiring is required by the learning scheme. Measurements on an experimental chip set are presented.
本文介绍了一种用于人工神经网络的模拟、可级联的CMOS芯片组。该芯片组（一个突触芯片和一个神经元芯片）在任意大小和拓扑结构的全并行、分层、前馈网络中提供片上反向传播学习。与没有学习方案的系统相比，该学习方案在突触部位无需额外电路，在神经元部位只需复杂度与神经元相当的额外电路。此外，该学习方案无需额外布线。文中还给出了对实验芯片组的测量结果。
