Patterson William R, Song Yoon-Kyu, Bull Christopher W, Ozden Ilker, Deangellis Andrew P, Lay Christopher, McKay J Lucas, Nurmikko Arto V, Donoghue John D, Connors Barry W
Division of Engineering, Brown University, Providence, RI 02912, USA.
IEEE Trans Biomed Eng. 2004 Oct;51(10):1845-53. doi: 10.1109/TBME.2004.831521.
We have designed, fabricated, and characterized a microminiaturized "neuroport" for brain implantable neuroprosthesis applications, using an analog CMOS integrated circuit and a silicon based microelectrode array. An ultra-low power, low-noise CMOS preamplifier array with integral multiplexing was designed to accommodate stringent thermal and electrophysiological requirements for implantation in the brain, and a hybrid integration approach was developed to fabricate a functional microminiaturized neuroprobe device. Measurements showed that our fully scalable 16-channel CMOS amplifier chip had an average gain of 44 dB, bandwidth from 10 Hz to 7.3 kHz, and an equivalent input noise of approximately 9 microVrms with an average power consumption per preamplifier of 52 microW, which is consistent with simulation results. As a proof-of-concept demonstration, we have measured local field potentials from thalamocortical brain slices of rats, showing oscillatory behavior with an amplitude about 0.5 mV and a period ranging 80-120 ms. The results suggest that the hybrid integrated neuroport can form a prime platform for the development of a next level microminiaturized neural interface to the brain in a single implantable unit.
我们设计、制造并表征了一种用于脑植入式神经假体应用的微型化“神经端口”,采用了模拟CMOS集成电路和基于硅的微电极阵列。设计了一种具有集成多路复用功能的超低功耗、低噪声CMOS前置放大器阵列,以满足植入大脑的严格热学和电生理要求,并开发了一种混合集成方法来制造功能性微型神经探针装置。测量结果表明,我们完全可扩展的16通道CMOS放大器芯片平均增益为44 dB,带宽为10 Hz至7.3 kHz,等效输入噪声约为9 μVrms,每个前置放大器的平均功耗为52 μW,这与仿真结果一致。作为概念验证演示,我们测量了大鼠丘脑皮质脑切片的局部场电位,显示出振荡行为,幅度约为0.5 mV,周期为80 - 120 ms。结果表明,混合集成神经端口可以在单个可植入单元中形成一个用于开发下一代微型化脑神经接口的主要平台。