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自对准全印刷聚合物薄膜晶体管的尺寸缩小

Downscaling of self-aligned, all-printed polymer thin-film transistors.

作者信息

Noh Yong-Young, Zhao Ni, Caironi Mario, Sirringhaus Henning

机构信息

Cavendish Laboratory, University of Cambridge, JJ Thomson Avenue, Cambridge CB3 0HE, UK.

出版信息

Nat Nanotechnol. 2007 Dec;2(12):784-9. doi: 10.1038/nnano.2007.365. Epub 2007 Nov 18.

DOI:10.1038/nnano.2007.365
PMID:18654432
Abstract

Printing is an emerging approach for low-cost, large-area manufacturing of electronic circuits, but it has the disadvantages of poor resolution, large overlap capacitances, and film thickness limitations, resulting in slow circuit speeds and high operating voltages. Here, we demonstrate a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100-400 nm. The use of a crosslinkable polymer gate dielectric with 30-50 nm thickness ensures that basic scaling requirements are fulfilled and that operating voltages are below 5 V. The device architecture minimizes contact resistance effects, enabling clean scaling of transistor current with channel length. A self-aligned gate configuration minimizes parasitic overlap capacitance to values as low as 0.2-0.6 pF mm(-1), and allows transition frequencies of fT = 1.6 MHz to be reached. Our self-aligned process provides a way to improve the performance of printed organic transistor circuits by downscaling, while remaining compatible with the requirements of large-area, flexible electronics manufacturing.

摘要

印刷是一种用于低成本、大面积制造电子电路的新兴方法,但它存在分辨率低、重叠电容大以及薄膜厚度受限等缺点,导致电路速度慢且工作电压高。在此,我们展示了一种自对准印刷方法,该方法可将印刷有机薄膜晶体管的沟道长度缩小至100 - 400纳米。使用厚度为30 - 50纳米的可交联聚合物栅极电介质可确保满足基本的缩小要求,且工作电压低于5伏。该器件架构可将接触电阻效应降至最低,使晶体管电流能随沟道长度实现清晰的缩小。自对准栅极配置可将寄生重叠电容降至低至0.2 - 0.6皮法/毫米(-1)的值,并能达到1.6兆赫的过渡频率。我们的自对准工艺提供了一种通过缩小尺寸来提高印刷有机晶体管电路性能的方法,同时仍与大面积、柔性电子制造的要求兼容。

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