Chen Tung-Chien, Liu Wentai, Chen Liang-Gee
University of California, Santa Cruz, CA, USA.
Annu Int Conf IEEE Eng Med Biol Soc. 2008;2008:3192-5. doi: 10.1109/IEMBS.2008.4649882.
On-chip spike detection and principal component analysis (PCA) sorting hardware in an integrated multi-channel neural recording system is highly desired to ease the bandwidth bottleneck from high-density microelectrode array implanted in the cortex. In this paper, we propose the first leading eigenvector generator, the key hardware module of PCA, to enable the whole framework. Based on the iterative eigenvector distilling algorithm, the proposed flipped structure enables the low cost and low power implementation by discarding the division and square root hardware units. Further, the proposed adaptive level shifting scheme optimizes the accuracy and area trade off by dynamically increasing the quantization parameter according to the signal level.With the specification of four principal components/channel, 32 samples/spike, and nine bits/sample, the proposed hardware can train 312 channels per minute with 1MHz operation frequency. 0.13 mm(2) silicon area and 282microW power consumption are required in 90 nm 1P9M CMOS process.
集成多通道神经记录系统中用于片上尖峰检测和主成分分析（PCA）分类的硬件非常需要，以缓解植入皮层的高密度微电极阵列带来的带宽瓶颈。在本文中，我们提出了首个主导特征向量生成器，即PCA的关键硬件模块，以实现整个框架。基于迭代特征向量提取算法，所提出的翻转结构通过舍弃除法和平方根硬件单元实现了低成本和低功耗。此外，所提出的自适应电平转换方案通过根据信号电平动态增加量化参数来优化精度和面积的权衡。按照每个通道四个主成分、每个尖峰32个样本以及每个样本9位的规格，所提出的硬件在1MHz工作频率下每分钟可训练312个通道。在90nm 1P9M CMOS工艺中，需要0.13mm²的硅面积和282μW的功耗。
