Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology, School of Physics, University of Melbourne, Victoria 3010, Australia.
Nanotechnology. 2013 Apr 12;24(14):145304. doi: 10.1088/0957-4484/24/14/145304. Epub 2013 Mar 18.
Solid state electronic devices fabricated in silicon employ many ion implantation steps in their fabrication. In nanoscale devices deterministic implants of dopant atoms with high spatial precision will be needed to overcome problems with statistical variations in device characteristics and to open new functionalities based on controlled quantum states of single atoms. However, to deterministically place a dopant atom with the required precision is a significant technological challenge. Here we address this challenge with a strategy based on stepped nanostencil lithography for the construction of arrays of single implanted atoms. We address the limit on spatial precision imposed by ion straggling in the nanostencil-fabricated with the readily available focused ion beam milling technique followed by Pt deposition. Two nanostencils have been fabricated; a 60 nm wide aperture in a 3 μm thick Si cantilever and a 30 nm wide aperture in a 200 nm thick Si3N4 membrane. The 30 nm wide aperture demonstrates the fabricating process for sub-50 nm apertures while the 60 nm aperture was characterized with 500 keV He(+) ion forward scattering to measure the effect of ion straggling in the collimator and deduce a model for its internal structure using the GEANT4 ion transport code. This model is then applied to simulate collimation of a 14 keV P(+) ion beam in a 200 nm thick Si3N4 membrane nanostencil suitable for the implantation of donors in silicon. We simulate collimating apertures with widths in the range of 10-50 nm because we expect the onset of J-coupling in a device with 30 nm donor spacing. We find that straggling in the nanostencil produces mis-located implanted ions with a probability between 0.001 and 0.08 depending on the internal collimator profile and the alignment with the beam direction. This result is favourable for the rapid prototyping of a proof-of-principle device containing multiple deterministically implanted dopants.
在硅基制造的固态电子器件中，许多制造步骤都需要进行离子注入。在纳米器件中，需要具有高精度空间定位的掺杂原子确定性注入，以克服器件特性的统计变化问题，并基于单个原子的可控量子态开拓新的功能。然而，要以所需精度确定性地放置掺杂原子，这是一个重大的技术挑战。在这里，我们通过基于分步纳米掩模光刻的策略来解决这一挑战，该策略用于构建单注入原子的阵列。我们通过聚焦离子束铣削技术来解决纳米掩模制造过程中离子扩散限制的空间精度问题，随后进行 Pt 沉积。我们制造了两个纳米掩模；一个是 3μm 厚 Si 悬臂上的 60nm 宽孔径，另一个是 200nm 厚 Si3N4 膜上的 30nm 宽孔径。30nm 宽的孔径展示了用于制造 50nm 以下孔径的制造工艺，而 60nm 孔径则通过 500keV He(+)离子前向散射进行了表征，以测量准直器中离子扩散的影响，并使用 GEANT4 离子传输代码推导出其内部结构的模型。然后，该模型用于模拟在适用于硅中施主注入的 200nm 厚 Si3N4 膜纳米掩模中，14keV P(+)离子束的准直。我们模拟了宽度在 10-50nm 范围内的准直孔径，因为我们预计在具有 30nm 施主间距的器件中会出现 J 耦合。我们发现，纳米掩模中的扩散会导致注入离子错位，其概率在 0.001 到 0.08 之间，具体取决于内部准直器的轮廓和与光束方向的对准。对于包含多个确定性注入掺杂剂的原理验证设备的快速原型制作，这一结果是有利的。
