Bozzola Angelo, Carroll Lee, Gerace Dario, Cristiani Ilaria, Andreani Lucio Claudio
Opt Express. 2015 Jun 15;23(12):16289-304. doi: 10.1364/OE.23.016289.
We present a theoretical optimisation of 1D apodized grating couplers in a "pure" Silicon-On-Insulator (SOI) architecture, i.e. without any bottom reflector element, by means of a general mutative method. We perform a comprehensive 2D Finite Difference Time Domain study of chirped and apodized grating couplers in 220 nm SOI, and demonstrate that the global maximum coupling efficiency in that platform is capped to 65% (-1.9 dB). Moving to designs with thicker Si-layers, we identify a new record design in 340 nm SOI, with a simulated coupling efficiency of 89% (-0.5 dB). Going to thicker Si layers does not further improve the efficiency, implying that -0.5 dB may be a global maximum for a grating coupler in SOI without a bottom-reflector. Even after allowing for 193 nm UV-lithographic fabrication constraints, the 340 nm design still offers -0.7 dB efficiency. These new apodized designs are the first pure SOI couplers compatible with deep-UV lithography to offer better than -1 dB insertion losses. With only very minor changes to existing deposition and lithography recipes, they are compatible with the multi-project wafer runs already offered by Si-Photonics foundries.
我们通过一种通用的变分方法，对“纯”绝缘体上硅（SOI）结构中的一维变迹光栅耦合器进行了理论优化，即不包含任何底部反射器元件。我们对220nm SOI中的啁啾和变迹光栅耦合器进行了全面的二维时域有限差分研究，并证明该平台中的全局最大耦合效率限制为65%（-1.9dB）。转向具有更厚硅层的设计时，我们在340nm SOI中确定了一种新的创纪录设计，模拟耦合效率为89%（-0.5dB）。增加硅层厚度并不会进一步提高效率，这意味着对于没有底部反射器的SOI中的光栅耦合器，-0.5dB可能是全局最大值。即使考虑到193nm紫外光刻制造限制，340nm设计仍能提供-0.7dB的效率。这些新的变迹设计是首批与深紫外光刻兼容的纯SOI耦合器，其插入损耗优于-1dB。只需对现有沉积和光刻工艺进行非常小的更改，它们就与硅光子学代工厂已经提供的多项目晶圆运行兼容。
