Department of Electrical and Information Technology, Lund University , Box 118, 221 00 Lund, Sweden.
Department of Electrical and Computer Engineering, University of California , Santa Barbara, California 93106, United States.
Nano Lett. 2017 Oct 11;17(10):6006-6010. doi: 10.1021/acs.nanolett.7b02251. Epub 2017 Sep 14.
III-V compound semiconductors offer a path to continue Moore's law due to their excellent electron transport properties. One major challenge, integrating III-V's on Si, can be addressed by using vapor-liquid-solid grown vertical nanowires. InAs is an attractive material due to its superior mobility, although InAs metal-oxide-semiconductor field-effect transistors (MOSFETs) typically suffer from band-to-band tunneling caused by its narrow band gap, which increases the off-current and therefore the power consumption. In this work, we present vertical heterostructure InAs/InGaAs nanowire MOSFETs with low off-currents provided by the wider band gap material on the drain side suppressing band-to-band tunneling. We demonstrate vertical III-V MOSFETs achieving off-current below 1 nA/μm while still maintaining on-performance comparable to InAs MOSFETs; therefore, this approach opens a path to address not only high-performance applications but also Internet-of-Things applications that require low off-state current levels.
III-V 族化合物半导体由于其优异的电子输运性能，为继续摩尔定律提供了一条途径。在硅上集成 III-V 族半导体的一个主要挑战可以通过使用汽液固生长的垂直纳米线来解决。由于其较高的迁移率，InAs 是一种很有吸引力的材料，尽管由于其较窄的带隙，InAs 金属氧化物半导体场效应晶体管 (MOSFET) 通常会受到带带隧穿的影响，这会增加漏电流，从而增加功耗。在这项工作中，我们提出了具有低漏电流的垂直异质结构 InAs/InGaAs 纳米线 MOSFET，通过在漏极侧使用较宽带隙材料来抑制带带隧穿。我们展示了垂直 III-V MOSFET，其漏电流低于 1 nA/μm，同时仍保持与 InAs MOSFET 相当的导通性能；因此，这种方法不仅为高性能应用，也为需要低关态电流水平的物联网应用开辟了一条道路。
