Multilayer Graphene-WSe Heterostructures for WSe Transistors.

Two-dimensional (2D) materials are drawing growing attention for next-generation electronics and optoelectronics owing to its atomic thickness and unique physical properties. One of the challenges posed by 2D materials is the large source/drain (S/D) series resistance due to their thinness, which may be resolved by thickening the source and drain regions. Recently explored lateral graphene-MoS1-3 and graphene-WS1,4 heterostructures shed light on resolving the mentioned issues owing to their superior ohmic contact behaviors. However, recently reported field-effect transistors (FETs) based on graphene-TMD heterostructures have only shown n-type characteristics. The lack of p-type transistor limits their applications in complementary metal-oxide semiconductor electronics. In this work, we demonstrate p-type FETs based on graphene-WSe lateral heterojunctions grown with the scalable CVD technique. Few-layer WSe is overlapped with the multilayer graphene (MLG) at MLG-WSe junctions such that the contact resistance is reduced. Importantly, the few-layer WSe only forms at the junction region while the channel is still maintained as a WSe monolayer for transistor operation. Furthermore, by imposing doping to graphene S/D, 2 orders of magnitude enhancement in I/I ratio to ∼10 and the unipolar p-type characteristics are obtained regardless of the work function of the metal in ambient air condition. The MLG is proposed to serve as a 2D version of emerging raised source/drain approach in electronics.