Bassoli Marco, Bianchi Valentina, De Munari Ilaria
Department of Engineering and Architecture, University of Parma, Parco Area delle Scienze, 181/A, 43124 Parma, Italy.
Sensors (Basel). 2020 Mar 2;20(5):1362. doi: 10.3390/s20051362.
Recent research in wearable sensors have led to the development of an advanced platform capable of embedding complex algorithms such as machine learning algorithms, which are known to usually be resource-demanding. To address the need for high computational power, one solution is to design custom hardware platforms dedicated to the specific application by exploiting, for example, Field Programmable Gate Array (FPGA). Recently, model-based techniques and automatic code generation have been introduced in FPGA design. In this paper, a new model-based floating-point accumulation circuit is presented. The architecture is based on the state-of-the-art delayed buffering algorithm. This circuit was conceived to be exploited in order to compute the kernel function of a support vector machine. The implementation of the proposed model was carried out in Simulink, and simulation results showed that it had better performance in terms of speed and occupied area when compared to other solutions. To better evaluate its figure, a practical case of a polynomial kernel function was considered. Simulink and VHDL post-implementation timing simulations and measurements on FPGA confirmed the good results of the stand-alone accumulator.
近期可穿戴传感器的研究催生了一个先进平台，该平台能够嵌入复杂算法，如机器学习算法，而这类算法通常对资源需求较高。为满足对高计算能力的需求，一种解决方案是通过利用例如现场可编程门阵列（FPGA）来设计专用于特定应用的定制硬件平台。最近，基于模型的技术和自动代码生成已被引入FPGA设计中。本文提出了一种新的基于模型的浮点累加电路。该架构基于最先进的延迟缓冲算法。此电路旨在用于计算支持向量机的核函数。所提模型在Simulink中实现，仿真结果表明，与其他解决方案相比，它在速度和占用面积方面具有更好的性能。为更好地评估其性能，考虑了多项式核函数的一个实际案例。在FPGA上进行的Simulink和VHDL实现后定时仿真及测量证实了独立累加器的良好结果。
