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用于提高MoS晶体管电应力稳定性的盖帽层

Capping Layers to Improve the Electrical Stress Stability of MoS Transistors.

作者信息

Doherty James L, Noyce Steven G, Cheng Zhihui, Abuzaid Hattan, Franklin Aaron D

机构信息

Department of Electrical and Computer Engineering, Duke University, Durham, North Carolina 27708, United States.

Department of Chemistry, Duke University, Durham, North Carolina 27708, United States.

出版信息

ACS Appl Mater Interfaces. 2020 Aug 5;12(31):35698-35706. doi: 10.1021/acsami.0c08647. Epub 2020 Jul 27.

Abstract

Two-dimensional (2D) materials offer exciting possibilities for numerous applications, including next-generation sensors and field-effect transistors (FETs). With their atomically thin form factor, it is evident that molecular activity at the interfaces of 2D materials can shape their electronic properties. Although much attention has focused on engineering the contact and dielectric interfaces in 2D material-based transistors to boost their drive current, less is understood about how to tune these interfaces to improve the long-term stability of devices. In this work, we evaluated molybdenum disulfide (MoS) transistors under continuous electrical stress for periods lasting up to several days. During stress in ambient air, we observed temporary threshold voltage shifts that increased at higher gate voltages or longer stress durations, correlating to changes in interface trap states (Δ) of up to 10 cm. By modifying the device to include either SU-8 or AlO as an additional dielectric capping layer on top of the MoS channel, we were able to effectively reduce or even eliminate this unstable behavior. However, we found this encapsulating material must be selected carefully, as certain choices actually amplified instability or compromised device yield, as was the case for AlO, which reduced yield by 20% versus all other capping layers. Further refining these strategies to preserve stability in 2D devices will be crucial for their continued integration into future technologies.

摘要

二维(2D)材料为众多应用提供了令人兴奋的可能性,包括下一代传感器和场效应晶体管(FET)。由于其原子级薄的外形尺寸,二维材料界面处的分子活性显然会影响其电子特性。尽管人们将大量注意力集中在设计基于二维材料的晶体管中的接触和介电界面以提高其驱动电流上,但对于如何调整这些界面以提高器件的长期稳定性却了解较少。在这项工作中,我们对二硫化钼(MoS)晶体管在持续电应力下进行了长达数天的评估。在环境空气中施加应力期间,我们观察到临时阈值电压偏移,在较高栅极电压或较长应力持续时间下会增加,这与界面陷阱态(Δ)高达10厘米的变化相关。通过修改器件,在MoS沟道顶部添加SU-8或AlO作为额外的介电覆盖层,我们能够有效减少甚至消除这种不稳定行为。然而,我们发现必须谨慎选择这种封装材料,因为某些选择实际上会放大不稳定性或降低器件成品率,例如AlO,与所有其他覆盖层相比,其成品率降低了20%。进一步完善这些策略以保持二维器件的稳定性对于它们持续融入未来技术至关重要。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/05b4/7895421/905f0ce0f6cc/nihms-1669799-f0002.jpg

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