Bussolotti Fabio, Yang Jing, Kawai Hiroyo, Wong Calvin Pei Yu, Goh Kuan Eng Johnson
Institute of Materials Research & Engineering (IMRE), Agency for Science, Technology, and Research (A*STAR), 2 Fusionopolis Way, #08-03 Innovis, Singapore 138634, Singapore.
Institute of High Performance Computing (IHPC), Agency for Science, Technology and Research (A*STAR), 1 Fusionopolis Way, #16-16 Connexis, Singapore 138632, Singapore.
ACS Nano. 2021 Feb 23;15(2):2686-2697. doi: 10.1021/acsnano.0c07982. Epub 2021 Jan 27.
Making electrical contacts to semiconducting transition metal dichalcogenides (TMDCs) represents a major bottleneck for high device performance, often manifesting as strong Fermi level pinning and high contact resistance. Despite intense ongoing research, the mechanism by which lattice defects in TMDCs impact the transport properties across the contact-TMDC interface remains unsettled. Here we study the impact of S-vacancies on the electronic properties at a MoS monolayer interfaced with graphite by photoemission spectroscopy, where the defect density is selectively controlled by Ar sputtering. A clear reduction of the MoS core level and valence band binding energies is observed as the defect density increases. The experimental results are explained in terms of (i) gap states' energy distribution and (ii) S-vacancies' electrostatic disorder effect. Our model indicates that the Fermi level pinning at deep S-vacancy gap states is the origin of the commonly reported large electron injection barrier (∼0.5 eV) at the MoS ML interface with low work function metals. At the contact with high work function electrodes, S-vacancies do not significantly affect the hole injection barrier, which is intrinsically favored by Fermi level pinning at shallow occupied gap states. Our results clarify the importance of S-vacancies and electrostatic disorder in TMDC-based electronic devices, which could lead to strategies for optimizing device performance and production.
与半导体过渡金属二硫属化物(TMDCs)形成电接触是实现高器件性能的一个主要瓶颈,通常表现为强烈的费米能级钉扎和高接触电阻。尽管目前正在进行深入研究,但TMDCs中的晶格缺陷影响跨接触-TMDC界面传输特性的机制仍未确定。在此,我们通过光电子能谱研究了与石墨界面的MoS单层中S空位对电子特性的影响,其中缺陷密度通过氩溅射选择性地控制。随着缺陷密度增加,观察到MoS核心能级和价带结合能明显降低。实验结果从(i)能隙态的能量分布和(ii)S空位的静电无序效应方面进行了解释。我们的模型表明,在深S空位能隙态处的费米能级钉扎是在MoS单层与低功函数金属界面处普遍报道的大电子注入势垒(约0.5 eV)的起源。在与高功函数电极接触时,S空位对空穴注入势垒没有显著影响,空穴注入势垒本质上受浅占据能隙态处的费米能级钉扎所青睐。我们的结果阐明了S空位和静电无序在基于TMDC的电子器件中的重要性,这可能会带来优化器件性能和生产的策略。