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具有可调截止频率的 AC 耦合 CMOS 神经放大器中的非线性失真分析与减小。

Analysis and Reduction of Nonlinear Distortion in AC-Coupled CMOS Neural Amplifiers with Tunable Cutoff Frequencies.

机构信息

Faculty of Physics and Applied Computer Science, AGH University of Science and Technology, 30-059 Kraków, Poland.

出版信息

Sensors (Basel). 2021 Apr 30;21(9):3116. doi: 10.3390/s21093116.

Abstract

Integrated CMOS neural amplifiers are key elements of modern large-scale neuroelectronic interfaces. The neural amplifiers are routinely AC-coupled to electrodes to remove the DC voltage. The large resistances required for the AC coupling circuit are usually realized using MOSFETs that are nonlinear. Specifically, designs with tunable cutoff frequency of the input high‑pass filter may suffer from excessive nonlinearity, since the gate-source voltages of the transistors forming the pseudoresistors vary following the signal being amplified. Consequently, the nonlinear distortion in such circuits may be high for signal frequencies close to the cutoff frequency of the input filter. Here we propose a simple modification of the architecture of a tunable AC-coupled amplifier, in which the bias voltages of the transistors forming the pseudoresistor are kept constant independently of the signal levels, what results in significantly improved linearity. Based on numerical simulations of the proposed circuit designed in 180 nm technology we analyze the Total Harmonic Distortion levels as a function of signal frequency and amplitude. We also investigate the impact of basic amplifier parameters-gain, cutoff frequency of the AC coupling circuit, and silicon area-on the distortion and noise performance. The post-layout simulations of the complete test ASIC show that the distortion is very significantly reduced at frequencies near the cutoff frequency, when compared to the commonly used circuits. The THD values are below 1.17% for signal frequencies 1 Hz-10 kHz and signal amplitudes up to 10 mV peak-to-peak. The preamplifier area is only 0.0046 mm and the noise is 8.3 µV in the 1 Hz-10 kHz range. To our knowledge this is the first report on a CMOS neural amplifier with systematic characterization of THD across complete range of frequencies and amplitudes of neuronal signals recorded by extracellular electrodes.

摘要

集成 CMOS 神经放大器是现代大规模神经电子接口的关键元件。神经放大器通常通过交流耦合到电极上来去除直流电压。交流耦合电路所需的大电阻通常使用非线性 MOSFET 来实现。具体来说,具有可调输入高通滤波器截止频率的设计可能会受到过度非线性的影响,因为形成伪电阻的晶体管的栅源电压会随被放大的信号而变化。因此,对于接近输入滤波器截止频率的信号频率,此类电路中的非线性失真可能会很高。在这里,我们提出了一种可调谐交流耦合放大器架构的简单修改,其中形成伪电阻的晶体管的偏置电压独立于信号电平保持恒定,从而显著提高了线性度。基于在 180nm 技术中设计的提议电路的数值模拟,我们分析了总谐波失真水平作为信号频率和幅度的函数。我们还研究了基本放大器参数-增益、交流耦合电路的截止频率以及硅面积-对失真和噪声性能的影响。完整测试 ASIC 的后布局模拟表明,与常用电路相比,在接近截止频率的频率下,失真显著降低。当信号频率为 1Hz-10kHz 且信号幅度高达 10mV 峰峰值时,THD 值低于 1.17%。前置放大器面积仅为 0.0046mm,噪声在 1Hz-10kHz 范围内为 8.3µV。据我们所知,这是第一个关于具有系统地在由体外电极记录的神经元信号的完整频率和幅度范围内对 THD 进行特征化的 CMOS 神经放大器的报告。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/f9dd/8125415/154b11bd56c1/sensors-21-03116-g001.jpg

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