Yang Yejin, Park Young-Soo, Son Jaemin, Cho Kyoungah, Kim Sangsig
Department of Semiconductor Systems Engineering, Korea University, Seoul, Republic of Korea.
Department of Electrical Engineering, Korea University, 145 Anam-ro, Seongbuk-gu, Seoul, 02841, Republic of Korea.
Sci Rep. 2021 Sep 20;11(1):18650. doi: 10.1038/s41598-021-98182-7.
In this study, we examine the electrical characteristics of silicon nanowire feedback field-effect transistors (FBFETs) with interface trap charges between the channel and gate oxide. The band diagram, I-V characteristics, memory window, and operation were analyzed using a commercial technology computer-aided design simulation. In an n-channel FBFET, the memory window narrows (widens) from 5.47 to 3.59 V (9.24 V), as the density of the positive (negative) trap charges increases. In contrast, in the p-channel FBFET, the memory window widens (narrows) from 5.38 to 7.38 V (4.18 V), as the density of the positive (negative) trap charges increases. Moreover, we investigate the difference in the output drain current based on the interface trap charges during the memory operation.
在本研究中，我们研究了沟道与栅氧化层之间存在界面陷阱电荷的硅纳米线反馈场效应晶体管（FBFET）的电学特性。使用商业技术计算机辅助设计模拟分析了能带图、I-V特性、存储窗口和操作。在n沟道FBFET中，随着正（负）陷阱电荷密度的增加，存储窗口从5.47 V缩小（扩大）至3.59 V（9.24 V）。相比之下，在p沟道FBFET中，随着正（负）陷阱电荷密度的增加，存储窗口从5.38 V扩大（缩小）至7.38 V（4.18 V）。此外，我们研究了存储操作期间基于界面陷阱电荷的输出漏极电流差异。
