Kim Jihyun, Jung Myeongjin, Lim Dong Un, Rhee Dongjoon, Jung Sung Hyeon, Cho Hyung Koun, Kim Han-Ki, Cho Jeong Ho, Kang Joohoon
School of Advanced Materials Science and Engineering, Sungkyunkwan University (SKKU), Suwon 16419, Republic of Korea.
Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul 03722, Republic of Korea.
Nano Lett. 2022 Jan 26;22(2):570-577. doi: 10.1021/acs.nanolett.1c02947. Epub 2021 Nov 15.
Multi-valued logic gates are demonstrated on solution-processed molybdenum disulfide (MoS) thin films. A simple chemical doping process is added to the conventional transistor fabrication procedure to locally increase the work function of MoS by decreasing sulfur vacancies. The resulting device exhibits pseudo-heterojunctions comprising as-processed MoS and chemically treated MoS (c-MoS). The energy-band misalignment of MoS and c-MoS results in a sequential activation of the MoS and c-MoS channel areas under a gate voltage sweep, which generates a stable intermediate state for ternary operation. Current levels and turn-on voltages for each state can be tuned by modulating the device geometries, including the channel thickness and length. The optimized ternary transistors are incorporated to demonstrate various ternary logic gates, including the inverter, NMIN, and NMAX gates.
在溶液处理的二硫化钼(MoS)薄膜上展示了多值逻辑门。在传统晶体管制造工艺中添加了一个简单的化学掺杂过程,通过减少硫空位来局部提高MoS的功函数。所得器件呈现出由加工后的MoS和化学处理的MoS(c-MoS)组成的伪异质结。MoS和c-MoS的能带失配导致在栅极电压扫描下MoS和c-MoS沟道区域的顺序激活,从而产生用于三值操作的稳定中间状态。通过调制器件几何结构,包括沟道厚度和长度,可以调整每种状态的电流水平和开启电压。将优化后的三值晶体管用于演示各种三值逻辑门,包括反相器、NMIN和NMAX门。