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可重构二进制和三值逻辑器件实现逻辑状态调制。

Reconfigurable binary and ternary logic devices enabling logic state modulation.

作者信息

Kwon Yonghyun Albert, Park Su Bin, Kim Jaeyeon, Yoo Youngjae, Lee Seung Woo, Cho Jeong Ho

机构信息

Department of Chemical and Biomolecular Engineering, Yonsei University, Seoul, Republic of Korea.

School of Chemical Engineering, Yeungnam University, Gyeongsan, Republic of Korea.

出版信息

Nat Commun. 2025 Jul 22;16(1):6740. doi: 10.1038/s41467-025-62116-y.

DOI:10.1038/s41467-025-62116-y
PMID:40695834
原文链接:https://pmc.ncbi.nlm.nih.gov/articles/PMC12284027/
Abstract

This paper reports a reconfigurable binary-ternary transistor with a controllable voltage range and current level for the intermediate logic state. The proposed functions were demonstrated using an indium-gallium-zinc-oxide channel with a dual-gate structure incorporating two types of dielectrics (with high and low capacitances). This asymmetric dual-gate structure exhibits two key characteristics. First, the threshold voltage can be adjusted by applying a voltage to the control gate opposing the input. Second, partial depletion occurs when the input gate's capacitance is insufficient, making the off current dependent on the control gate voltage. Two dual-gated channels were connected in series, with inputs applied to the low-capacitance gate of one channel and the high-capacitance gate of the other and the remaining gates served as control gates. This device configuration outputs three current regions: fully depleted (low), partially depleted (intermediate), and accumulated (high) channel currents, which were utilized as logic states for the ternary device. Moreover, the threshold voltage for each channel and the current from the partially depleted channel could be precisely controlled by biasing each control gate. This enables an adjustable voltage range and current level for the intermediate logic state, as well as reconfigurability between binary and ternary operations.

摘要

本文报道了一种具有可控电压范围和中间逻辑状态电流水平的可重构二进制-三进制晶体管。所提出的功能通过具有双栅结构的铟镓锌氧化物沟道得以证明,该双栅结构包含两种类型的电介质(具有高电容和低电容)。这种不对称双栅结构具有两个关键特性。首先,可以通过向与输入相反的控制栅施加电压来调节阈值电压。其次,当输入栅的电容不足时会发生部分耗尽,使得关断电流取决于控制栅电压。两个双栅沟道串联连接,输入分别施加到一个沟道的低电容栅和另一个沟道的高电容栅,其余的栅用作控制栅。这种器件配置输出三个电流区域:完全耗尽(低)、部分耗尽(中间)和积累(高)沟道电流,这些被用作三进制器件的逻辑状态。此外,通过对每个控制栅施加偏置,可以精确控制每个沟道的阈值电压以及部分耗尽沟道的电流。这使得中间逻辑状态具有可调节的电压范围和电流水平,以及二进制和三进制操作之间的可重构性。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/8b2e8566101c/41467_2025_62116_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/847ac32831b8/41467_2025_62116_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/7aa132e8ad35/41467_2025_62116_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/8f19a8c65b08/41467_2025_62116_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/8b2e8566101c/41467_2025_62116_Fig4_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/847ac32831b8/41467_2025_62116_Fig1_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/7aa132e8ad35/41467_2025_62116_Fig2_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/8f19a8c65b08/41467_2025_62116_Fig3_HTML.jpg
https://cdn.ncbi.nlm.nih.gov/pmc/blobs/276e/12284027/8b2e8566101c/41467_2025_62116_Fig4_HTML.jpg

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本文引用的文献

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Adv Mater. 2023 Dec;35(51):e2307206. doi: 10.1002/adma.202307206. Epub 2023 Nov 16.
2
A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors.基于漏极对准浮栅异质结晶体管的可重构二进制/三进制逻辑存储转换。
Nat Commun. 2023 Jun 23;14(1):3757. doi: 10.1038/s41467-023-39394-5.
3
Monolithic Tandem Vertical Electrochemical Transistors for Printed Multi-Valued Logic.
用于印刷多值逻辑的单片串联垂直电化学晶体管
Adv Mater. 2023 Mar;35(9):e2208757. doi: 10.1002/adma.202208757. Epub 2023 Jan 1.
4
Three-to-one analog signal modulation with a single back-bias-controlled reconfigurable transistor.采用单个背偏置控制的可重构晶体管实现的三比一模拟信号调制。
Nat Commun. 2022 Nov 17;13(1):7042. doi: 10.1038/s41467-022-34533-w.
5
Looking Beyond 0 and 1: Principles and Technology of Multi-Valued Logic Devices.超越0和1:多值逻辑器件的原理与技术
Adv Mater. 2022 Dec;34(51):e2108830. doi: 10.1002/adma.202108830. Epub 2022 Nov 17.
6
Vertically stacked, low-voltage organic ternary logic circuits including nonvolatile floating-gate memory transistors.包括非易失性浮栅存储器晶体管的垂直堆叠式低压有机三元逻辑电路。
Nat Commun. 2022 Apr 28;13(1):2305. doi: 10.1038/s41467-022-29756-w.
7
Area-Selective Chemical Doping on Solution-Processed MoS Thin-Film for Multi-Valued Logic Gates.用于多值逻辑门的溶液处理MoS薄膜上的区域选择性化学掺杂
Nano Lett. 2022 Jan 26;22(2):570-577. doi: 10.1021/acs.nanolett.1c02947. Epub 2021 Nov 15.
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Nanometer-Scale Ge-Based Adaptable Transistors Providing Programmable Negative Differential Resistance Enabling Multivalued Logic.基于锗的纳米级自适应晶体管,具备可编程负微分电阻,可实现多值逻辑。
ACS Nano. 2021 Nov 23;15(11):18135-18141. doi: 10.1021/acsnano.1c06801. Epub 2021 Oct 27.
9
Room-Temperature Negative Differential Resistance in Surface-Supported Metal-Organic Framework Vertical Heterojunctions.表面支撑的金属有机框架垂直异质结中的室温负微分电阻
Small. 2021 Sep;17(35):e2101475. doi: 10.1002/smll.202101475. Epub 2021 Jul 20.
10
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Adv Mater. 2021 Jul;33(29):e2101243. doi: 10.1002/adma.202101243. Epub 2021 Jun 1.