Wodnicki Robert, Kang Haochen, Li Di, Stephens Douglas N, Jung Hayong, Sun Yizhe, Chen Ruimin, Jiang Lai-Ming, Cabrera-Munoz Nestor E, Foiret Josquin, Zhou Qifa, Ferrara Katherine W
Department of Biomedical Engineering, University of Southern California, Los Angeles, CA, USA.
Department of Biomedical Engineering, University of California, Davis, Davis, CA, USA.
BME Front. 2022;2022. doi: 10.34133/2022/9870386. Epub 2022 Jun 30.
Large aperture ultrasonic arrays can be implemented by tiling together multiple pretested modules of high-density acoustic arrays with closely integrated multiplexing and buffering electronics to form a larger aperture with high yield. These modular arrays can be used to implement large 1.75D array apertures capable of focusing in elevation for uniform slice thickness along the axial direction which can improve image contrast. An important goal for large array tiling is obtaining high yield and sensitivity while reducing extraneous image artifacts. We have been developing tileable acoustic-electric modules for the implementation of large array apertures utilizing Application Specific Integrated Circuits (ASICs) implemented using 0.35 m high voltage (50 V) CMOS. Multiple generations of ASICs have been designed and tested. The ASICs were integrated with high-density transducer arrays for acoustic testing and imaging. The modules were further interfaced to a Verasonics Vantage imaging system and were used to image industry standard ultrasound phantoms. The first-generation modules comprise ASICs with both multiplexing and buffering electronics on-chip and have demonstrated a switching artifact which was visible in the images. A second-generation ASIC design incorporates low switching injection circuits which effectively mitigate the artifacts observed with the first-generation devices. Here, we present the architecture of the two ASIC designs and module types as well imaging results that demonstrate reduction in switching artifacts for the second-generation devices.
大孔径超声阵列可以通过将多个预先测试的高密度声学阵列模块与紧密集成的多路复用和缓冲电子器件拼接在一起实现,从而以高成品率形成更大的孔径。这些模块化阵列可用于实现大型1.75D阵列孔径,能够在仰角方向上聚焦,以沿轴向获得均匀的切片厚度,进而提高图像对比度。大阵列拼接的一个重要目标是在减少额外图像伪像的同时获得高成品率和灵敏度。我们一直在开发可拼接的声电模块,用于利用采用0.35微米高压(50V)CMOS实现的专用集成电路(ASIC)来实现大阵列孔径。已经设计并测试了多代ASIC。这些ASIC与高密度换能器阵列集成在一起用于声学测试和成像。这些模块进一步连接到Verasonics Vantage成像系统,并用于对行业标准超声体模进行成像。第一代模块包括片上同时具有多路复用和缓冲电子器件的ASIC,并且已经证明了在图像中可见的开关伪像。第二代ASIC设计采用了低开关注入电路,有效减轻了第一代器件中观察到的伪像。在此,我们展示了两种ASIC设计和模块类型的架构以及成像结果,这些结果表明第二代器件的开关伪像有所减少。