Wodnicki Robert, Kang Haochen, Chen Ruimin, Cabrera-Munoz Nestor E, Jung Hayong, Jiang Laiming, Foiret Josquin, Liu Yu, Chiu Victoria, Stephens Douglas N, Zhou Qifa, Ferrara Katherine W
IEEE Trans Ultrason Ferroelectr Freq Control. 2020 Feb;67(2):387-401. doi: 10.1109/TUFFC.2019.2944668. Epub 2019 Sep 30.
Tiled modular 2-D ultrasound arrays have the potential for realizing large apertures for novel diagnostic applications. This work presents an architecture for fabrication of tileable 2-D array modules implemented using 1-3 composites of high-bandwidth (BW) PIN-PMN-PT single-crystal piezoelectric material closely coupled with high-voltage CMOS application-specific integrated circuit (ASIC) electronics for buffering and multiplexing functions. The module, which is designed to be operated as a λ -pitch 1.75-D array, benefits from an improved electromechanical coupling coefficient and increased Curie temperature and is assembled directly on top of the ASIC silicon substrate using an interposer backing. The interposer consists of a novel 3-D printed acrylic frame that is filled with conducting and acoustically absorbing silver epoxy material. The ASIC comprises a high-voltage switching matrix with locally integrated buffering and is interfaced to a Verasonics Vantage 128, using a local field programmable gate array (FPGA) controller. Multiple prototype 5 ×6 element array modules have been fabricated by this process. The combined acoustic array and ASIC module was configured electronically by programming the switches to operate as a 1-D array with elements grouped in elevation for imaging and pulse-echo testing. The resulting array configuration had an average center frequency of 4.55 MHz, azimuthal element pitch of [Formula: see text], and exhibited average -20-dB pulsewidth of 592 ns and average -6-dB fractional BW of 77%.
平铺式模块化二维超声阵列有潜力为新型诊断应用实现大孔径。本文介绍了一种可平铺二维阵列模块的制造架构,该模块采用高带宽(BW)PIN-PMN-PT单晶压电材料的1-3复合材料,并与用于缓冲和复用功能的高压CMOS专用集成电路(ASIC)电子器件紧密耦合实现。该模块设计为以λ间距的1.75维阵列运行,受益于改进的机电耦合系数和提高的居里温度,并使用中介层背板直接组装在ASIC硅基板顶部。中介层由一个新型3D打印丙烯酸框架组成,框架内填充有导电且吸声的银环氧树脂材料。ASIC包括一个带有局部集成缓冲的高压开关矩阵,并通过本地现场可编程门阵列(FPGA)控制器与Verasonics Vantage 128接口。通过此工艺制造了多个原型5×6元件阵列模块。通过对开关进行编程,将声学阵列和ASIC模块组合配置为一维阵列,其元件在仰角方向分组,用于成像和脉冲回波测试。所得阵列配置的平均中心频率为4.55 MHz,方位角元件间距为[公式:见原文],平均-20 dB脉冲宽度为592 ns,平均-6 dB分数带宽为77%。