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使用可扩展的DNTT图案化工艺展示p型堆叠沟道三元逻辑器件。

Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process.

作者信息

Lee Yongsu, Kwon Heejin, Kim Seung-Mo, Lee Ho-In, Kim Kiyung, Lee Hae-Won, Kim So-Young, Hwang Hyeon Jun, Lee Byoung Hun

机构信息

Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Cheongam-Ro 77, Nam-Gu, Pohang, Gyeongbuk, 37673, Republic of Korea.

出版信息

Nano Converg. 2023 Mar 9;10(1):12. doi: 10.1186/s40580-023-00362-w.

Abstract

A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated. The stability of the DNTT stack-channel ternary logic switch device is confirmed by implementing a resistive-load ternary logic inverter circuit.

摘要

利用有机p型半导体二萘并[2,3-b:2',3'-f]噻吩并[3,2-b]噻吩(DNTT)展示了一种具有堆叠通道结构的p型三值逻辑器件。开发了一种基于光刻的图案化工艺来制造具有复杂有机半导体通道结构的微型电子器件。通过低温沉积工艺制造了两层带有隔离层的DNTT薄膜,并且首次展示了在中间电流状态下呈现零微分电导的p型三值逻辑开关特性。通过实现一个电阻负载三值逻辑反相器电路,证实了DNTT堆叠通道三值逻辑开关器件的稳定性。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/0093/9998751/53acec827767/40580_2023_362_Fig1_HTML.jpg

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