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一款16通道低功耗神经连接提取与锁相深部脑刺激系统芯片

A 16-Channel Low-Power Neural Connectivity Extraction and Phase-Locked Deep Brain Stimulation SoC.

作者信息

Shin Uisub, Ding Cong, Woods Virginia, Widge Alik S, Shoaran Mahsa

机构信息

Institute of Electrical and Micro Engineering, EPFL, 1202 Geneva, Switzerland, and the School of Electrical and Computer Engineering, Cornell University, Ithaca, NY 14853 USA.

Institute of Electrical and Micro Engineering and Neuro-X Institute, EPFL, 1202 Geneva, Switzerland.

出版信息

IEEE Solid State Circuits Lett. 2023;6:21-24. doi: 10.1109/lssc.2023.3238797. Epub 2023 Jan 23.

Abstract

Growing evidence suggests that phase-locked deep brain stimulation (DBS) can effectively regulate abnormal brain connectivity in neurological and psychiatric disorders. This letter therefore presents a low-power SoC with both neural connectivity extraction and phase-locked DBS capabilities. A 16-channel low-noise analog front-end (AFE) records local field potentials (LFPs) from multiple brain regions with precise gain matching. A novel low-complexity phase estimator and neural connectivity processor subsequently enable energy-efficient, yet accurate measurement of the instantaneous phase and cross-regional synchrony measures. Through flexible combination of neural biomarkers such as phase synchrony and spectral energy, a four-channel charge-balanced neurostimulator is triggered to treat various pathological brain conditions. Fabricated in 65-nm CMOS, the SoC occupies a silicon area of 2.24 mm and consumes 60 W, achieving over 60% power saving in neural connectivity extraction compared to the state-of-the-art. Extensive measurements demonstrate multi-channel LFP recording, real-time extraction of phase and neural connectivity measures, and phase-locked stimulation in rats.

摘要

越来越多的证据表明,锁相深部脑刺激(DBS)可以有效调节神经和精神疾病中的异常脑连接。因此,本文介绍了一种具有神经连接提取和锁相DBS功能的低功耗片上系统(SoC)。一个16通道的低噪声模拟前端(AFE)通过精确的增益匹配记录来自多个脑区的局部场电位(LFP)。随后,一种新型的低复杂度相位估计器和神经连接处理器实现了对瞬时相位和跨区域同步测量的节能且精确的测量。通过灵活组合诸如相位同步和频谱能量等神经生物标志物,触发一个四通道电荷平衡神经刺激器来治疗各种病理性脑部疾病。该SoC采用65纳米互补金属氧化物半导体(CMOS)工艺制造,占用硅面积为2.24平方毫米,功耗为60毫瓦,与现有技术相比,在神经连接提取方面实现了超过60%的节能。大量测量结果表明,该系统能够在大鼠中进行多通道LFP记录、实时提取相位和神经连接测量结果以及锁相刺激。

https://cdn.ncbi.nlm.nih.gov/pmc/blobs/bff1/9997065/59bc2299ec01/nihms-1871459-f0001.jpg

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