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二维铁电MoS/石墨烯晶体管的超快负电容转变

Ultrafast Negative Capacitance Transition for 2D Ferroelectric MoS/Graphene Transistor.

作者信息

Daw Debottam, Bouzid Houcine, Jung Moonyoung, Suh Dongseok, Biswas Chandan, Hee Lee Young

机构信息

Center for Integrated Nanostructure Physics, Institute for Basic Science, Sungkyunkwan University, Suwon, 16419, Republic of Korea.

Department of Energy Science, Sungkyunkwan University, Suwon, 16419, Republic of Korea.

出版信息

Adv Mater. 2024 Mar;36(13):e2304338. doi: 10.1002/adma.202304338. Epub 2024 Jan 4.

DOI:10.1002/adma.202304338
PMID:38153167
Abstract

Negative capacitance gives rise to subthreshold swing (SS) below the fundamental limit by efficient modulation of surface potential in transistors. While negative-capacitance transition is reported in polycrystalline Pb(ZrTi)O (PZT) and HfZrO (HZO) thin-films in few microseconds timescale, low SS is not persistent over a wide range of drain current when used instead of conventional dielectrics. In this work, the clear nano-second negative transition states in 2D single-crystal CuInPS (CIPS) flakes have been demonstrated by an alternative fast-transient measurement technique. Further, integrating this ultrafast NC transition with the localized density of states of Dirac contacts and controlled charge transfer in the CIPS/channel (MoS/graphene) a state-of-the-art device architecture, negative capacitance Dirac source drain field effect transistor (FET) is introduced. This yields an ultralow SS of 4.8 mV dec with an average sub-10 SS across five decades with on-off ratio exceeding 10, by simultaneous improvement of transport and body factors in monolayer MoS-based FET, outperforming all previous reports. This approach could pave the way to achieve ultralow-SS FETs for future high-speed and low-power electronics.

摘要

负电容通过对晶体管表面电势的有效调制,使亚阈值摆幅(SS)低于基本极限。虽然在几微秒的时间尺度内,多晶Pb(ZrTi)O(PZT)和HfZrO(HZO)薄膜中报道了负电容转变,但当替代传统电介质使用时,低SS在宽范围的漏极电流上并不持久。在这项工作中,通过一种替代的快速瞬态测量技术,在二维单晶CuInPS(CIPS)薄片中证明了清晰的纳秒级负转变状态。此外,将这种超快的负电容转变与狄拉克接触的局域态密度以及CIPS/沟道(MoS/石墨烯)中的可控电荷转移相结合,引入了一种先进的器件架构——负电容狄拉克源漏场效应晶体管(FET)。通过同时改善基于单层MoS的FET中的传输和体因子,这产生了4.8 mV/dec的超低SS,在五个数量级上平均亚阈值摆幅低于10 mV/dec,开/关比超过10,优于所有先前的报道。这种方法可为未来高速和低功耗电子学实现超低SS的FET铺平道路。

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